Camera stack not working on JP5.1

[akhil.veeraghanta]

Running into an issue w/ serdes and the camera drivers on JP5.1

# entries-in-buffer/entries-written: 21/21   #P:6
#
#                                _-----=> irqs-off
#                               / _----=> need-resched
#                              | / _---=> hardirq/softirq
#                              || / _--=> preempt-depth
#                              ||| /     delay
#           TASK-PID     CPU#  ||||   TIMESTAMP  FUNCTION
#              | |         |   ||||      |         |
     kworker/0:2-8810    [000] ....  1190.887204: rtcpu_string: tstamp:37895753648 id:0x04010000 str:"VM0 deactivating."
     kworker/0:2-8810    [000] ....  1201.037196: rtcpu_string: tstamp:38212741935 id:0x04010000 str:"VM0 activating."
  nvargus-daemon-10551   [003] ....  1201.237611: tegra_channel_open: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.237916: tegra_channel_close: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.244625: tegra_channel_open: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.244888: tegra_channel_close: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.280123: tegra_channel_open: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.280193: tegra_channel_close: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.280251: tegra_channel_open: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.280533: tegra_channel_close: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.280583: tegra_channel_open: vi-output, ox08b40 2-0030
  nvargus-daemon-10551   [003] ....  1201.280775: tegra_channel_close: vi-output, ox08b40 2-0030
 CaptureSchedule-10567   [004] ....  1201.477694: tegra_channel_open: vi-output, ox08b40 2-0030
 CaptureSchedule-10567   [003] ....  1201.481242: tegra_channel_set_power: ox08b40 2-0030 : 0x1
 CaptureSchedule-10567   [003] ....  1201.481255: camera_common_s_power: status : 0x1
 CaptureSchedule-10567   [003] ....  1201.508344: tegra_channel_set_power: 13e10000.host1x:nvcsi@15a00000- : 0x1
 CaptureSchedule-10567   [003] ....  1201.508352: csi_s_power: enable : 0x1
     kworker/0:2-8810    [000] ....  1201.547244: rtcpu_vinotify_event: tstamp:38228884185 cch:1 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:1223323673248 data:0xcd9ce50010000000
     kworker/0:2-8810    [000] ....  1201.547249: rtcpu_vinotify_event: tstamp:38228884358 cch:1 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:1223323684992 data:0x0000000031000001
     kworker/0:2-8810    [000] ....  1201.598250: rtcpu_vinotify_event: tstamp:38230240398 cch:1 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:1223357494656 data:0xcd9ce20010000000
     kworker/0:2-8810    [000] ....  1201.598256: rtcpu_vinotify_event: tstamp:38230240557 cch:1 vi:0 tag:VIFALC_TDSTATE channel:0x23 frame:0 vi_tstamp:1223357506560 data:0x0000000031000002

And it just gets indefinetly stuck

I’ve tried boosting clocks but not useful unfortunately. The deserializer and serializer are both reporting a VIDEO lock which means that things are “working” according to the serdes pair (MAX9295 and MAX9296)

Any tips on how to debug further?

[ 1540.505004] ox08b40 2-0030: ox08b40_set_mode: selecting mode 0
[ 1540.551783] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[ 1540.552024] [RCE] MIPI clock = 576000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[ 1540.552202] [RCE] ===== NVCSI Stream Configuration =====
[ 1540.552342] [RCE] stream_id: PP 0, csi_port: PORT A
[ 1540.552464] [RCE] Brick: PHY 0, Mode: D-PHY
[ 1540.552588] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[ 1540.552863] [RCE] Clock information:
[ 1540.552959] [RCE] MIPI clock rate: 576.00 MHz
[ 1540.553068] [RCE] T_HS settle: 0, T_CLK settle: 0
[ 1540.553184] [RCE] ======================================
[ 1540.553311] [RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[ 1540.553503] [RCE] nvcsi_calc_ths_settle ths_settle 19
[ 1540.553831] [RCE] nvcsi_calc_ths_settle ths_settle 19
[ 1540.554053] [RCE] nvcsi_calc_ths_settle ths_settle 19
[ 1540.554174] [RCE] nvcsi_calc_tclk_settle tclk_settle 33

The MIPI clock rate is 576.00MHZ here, but our PLL calclulations indicate that it should be at 1150. Where is the 576.00MHZ coming from? Is it sampling the actual clock rate it sees?

Any help would be appreciated, thank you!

[JerryChang]

@akhil.veeraghanta

Where is the 576.00MHZ coming from?

hello akhil.veeraghanta,

had you configure deserializer output data rate correctly? you should use this device tree property setting, serdes_pix_clk_hz.
you may see-also developer guide, SerDes Pixel Clock for reference.

BTW,
had you verified this camera driver, ox08b40 with SerDes chip on previous Jetpack release?

[akhil.veeraghanta]

@JerryChang

had you configure deserializer output data rate correctly? you should use this device tree property setting, serdes_pix_clk_hz …

I have this set to 1_200_000_000 which is the lane speed I have for the 4 lanes.

@JerryChang

had you verified this camera driver, ox08b40 with SerDes chip on previous Jetpack release?

It never worked properly, but I would get more data than nothing:

Camera driver doesn't work over GMSL

We have an omnivision sensor, for which we wrote a camera driver that works just fine over MIPI. When we plug the same camera into the serdes pair (MAX9295 ↔ MAX9296), it stops working with the following error kworker/1:3-1781 [001] .... 154.537183: rtcpu_vinotify_event: tstamp:4983168766 tag:FE channel:0x00 frame:0 vi_tstamp:4982877829 data:0x00000020 …

[akhil.veeraghanta]

I set the serdes pix clk to 1_200_000_000 and the mipi clock now says its 1_800_000_000?

[ 1200.915995] [RCE] NVCSILP clock rate = 204000000 Hz.
[ 1200.916194] [RCE] tegra_nvcsi_stream_set_config(vm0, stream=0, csi=0)
[ 1200.916339] [RCE] MIPI clock = 1800000 kHz, tHS-SETTLE = 0, tCLK-SETTLE = 0
[ 1200.916523] [RCE] ===== NVCSI Stream Configuration =====
[ 1200.916643] [RCE] stream_id: PP 0, csi_port: PORT A
[ 1200.916750] [RCE] Brick: PHY 0, Mode: D-PHY
[ 1200.916840] [RCE] Partition: CIL A, LP bypass: Enabled, Lanes: 4
[ 1200.917013] [RCE] Clock information:
[ 1200.917097] [RCE] MIPI clock rate: 1800.00 MHz
[ 1200.917196] [RCE] T_HS settle: 0, T_CLK settle: 0
[ 1200.917307] [RCE] ======================================
[ 1200.917452] [RCE] tegra_nvcsi_stream_open(vm0, stream=0, csi=0)
[ 1200.917590] [RCE] nvcsi_calc_ths_settle ths_settle 18
[ 1200.917717] [RCE] nvcsi_calc_ths_settle ths_settle 18
[ 1200.917835] [RCE] nvcsi_calc_ths_settle ths_settle 18
[ 1200.917977] [RCE] nvcsi_calc_tclk_settle tclk_settle 33
[ 1200.918992] [RCE] Deskew setup message sent for port 0 num_lane 4

Is that reading accurate? Are there any other factors going into that value?

update:
Using

serdes_pix_clk_hz = (deserializer output data rate in hertz) * (number of CSI lanes) / (bits per pixel).

in the link you sent, that value ends up being

serdes_pix_clk_hz = 1200 Mhz * 4 lanes / 12 bits per pixel = 4000mhz

there seems to be this logic

  3
  2     if (signal->phy_mode == CSI_PHY_MODE_DPHY) {
  1         /* MIPI clock rate */
143         signal->mipi_clock.val = rate / 2;
  1     } else if (signal->phy_mode == CSI_PHY_MODE_CPHY) {
  2         /* Symbol rate */
  3         signal->mipi_clock.val = rate * 7 / 16;
  4     } else {
  5         /* Data rate */
  6         signal->mipi_clock.val = rate;
  7     }

could you explain why its rate/2 as well?

Update

So setting serdes_pix_clk_hz using the forumla exactly and matching that speed on the deserializer, the cameras work and stream! Now im running into a different issue, but thank you so much!