Camera0 can get raw data by v4l2. but i exec jetson_multimedia_api/sample/09_camera_jpeg_capture failed!

Hi Jerry,

hello y2zwei,

may I know what’s the position property definition of rbpcv2_imx219_e.
are you having rbpcv2_imx219_e = front, and rbpcv2_imx219_c = rear?
if yes, please replace the position property of them for testing.

BTW,
how about using nvarguscamrasrc plugin to access the stream, is there any difference?
for example,

$ gst-launch-1.0 nvarguscamerasrc sensor-id=0 ! 'video/x-raw(memory:NVMM),width=1920, height=1080, framerate=30/1, format=NV12' ! nvoverlaysink -ev

1

hello y2zwei,

could you please share below for reference,
for example,
(1) $ dmesg | grep subdev
(2) $ ls /dev/video*
(3) $ v4l2-ctl -d /dev/video0 --list-formats-ext
(4) your full gst pipelines,

Hi Jerry,

hello y2zwei,

how about using the default resolution, 2592x1944. is it still failed and report no cameras available error?
please also check Sensor Pixel Clock session to review your pix_clk_hz settings, thanks

Hi Jerry,
rbpcv2_imx219_e and rbpcv2_imx219_c use same config of sensor.
and using the default resolution, 2592x1944. it’s still failed and report no cameras available error.

1

hello y2zwei,

are you able to arrange hardware resources to probe the MIPI signaling?
please access Tegra X1 TRM, you may also check the CSI registers to confirm its status.
for example, CSI_CILA_STATUS_0
thanks

Hi Jerry,
nano@nano-desktop:~$ v4l2-ctl -V --set-fmt-video=width=2592,height=1944,pixelformat=BA10 --set-ctrl bypass_mode=0 --stream-mmap --stream-count=1 -d /dev/video0 --stream-to=2592x1944_out.raw
<
Format Video Capture:
Width/Height : 2592/1944
Pixel Format : ‘BA10’
Field : None
Bytes per Line : 5184
Size Image : 10077696
Colorspace : sRGB
Transfer Function : Default (maps to sRGB)
YCbCr/HSV Encoding: Default (maps to ITU-R 601)
Quantization : Default (maps to Full Range)
Flags :

[ 1383.457733] ar0521 6-0036: camera_common_mclk_enable: enable MCLK with 24000000 Hz
[ 1383.457824] ar0521 6-0036: ar0521_power_on: power on
[ 1383.457833] ar0521 6-0036: ar0521_power_on: reset: 152
[ 1383.606138] ===ar0521_reg_30fps_init OK!===
[ 1383.606161] ar0521 6-0036: li===> tegracam_init_ctrl_ranges_by_mode: modeidx:0 num_modes:2
[ 1383.607000] ar0521 6-0036: ar0521_power_off: power off
[ 1383.607160] ar0521 6-0036: camera_common_mclk_disable: disable MCLK
[ 1383.607204] li===> tegra_vi2_power_on: ret:0
[ 1383.607231] ar0521 6-0036: camera_common_mclk_enable: enable MCLK with 24000000 Hz
[ 1383.607396] ar0521 6-0036: ar0521_power_on: power on
[ 1383.607415] ar0521 6-0036: ar0521_power_on: reset: 152
[ 1383.630872] li===> vi2_power_on: ret:0
[ 1383.633589] li===> v4l_s_fmt type:1 format:80853433832 width:2592 height:1944
[ 1383.633672] ar0521 6-0036: camera_common_try_fmt: size 2592 x 1944
[ 1383.633702] ar0521 6-0036: camera_common_try_fmt: use_sensor_mode_id 1
[ 1383.633733] li===> tegra_channel_fmt_align width:2592 height:1944 denominator:1 numerator:2 fmt_align:2 align:2 bpl:5184
[ 1383.633752] li===> tegra_channel_fmt_align bytesperline:0 bpl:5184
[ 1383.633773] li===> tegra_channel_fmt_align bpl :5184 32768 5184 stride_align:1 bytesperline:5184
[ 1383.633833] ar0521 6-0036: camera_common_s_fmt(12298) size 2592 x 1944
[ 1383.633873] ar0521 6-0036: camera_common_try_fmt: size 2592 x 1944
[ 1383.633896] ar0521 6-0036: camera_common_try_fmt: use_sensor_mode_id 1
[ 1383.633922] ar0521 6-0036: li===> tegracam_init_ctrl_ranges_by_mode: modeidx:0 num_modes:2
[ 1383.633953] li===> tegra_channel_fmt_align width:2592 height:1944 denominator:1 numerator:2 fmt_align:2 align:2 bpl:5184
[ 1383.633969] li===> tegra_channel_fmt_align bytesperline:5184 bpl:5184
[ 1383.633987] li===> tegra_channel_fmt_align bpl :5184 32768 5184 stride_align:1 bytesperline:5184
[ 1383.634680] li===> vb2_ioctl_reqbufs count:4 memory:1
[ 1383.654233] li===> v4l_querybuf memory:1
[ 1383.654237] li===> __fill_v4l2_buffer 2222222222222
[ 1383.654804] li===> __fill_v4l2_buffer 2222222222222
[ 1383.654809] li===> v4l_querybuf memory:1
[ 1383.654811] li===> __fill_v4l2_buffer 2222222222222
[ 1383.655426] li===> __fill_v4l2_buffer 2222222222222
[ 1383.655431] li===> v4l_querybuf memory:1
[ 1383.655432] li===> __fill_v4l2_buffer 2222222222222
[ 1383.656037] li===> __fill_v4l2_buffer 2222222222222
[ 1383.656041] li===> v4l_querybuf memory:1
[ 1383.656043] li===> __fill_v4l2_buffer 2222222222222
[ 1383.656631] li===> __fill_v4l2_buffer 2222222222222
[ 1383.656638] li===> vb2_ioctl_streamon
[ 1383.656648] li===> vi2_channel_start_streaming 1111111111
[ 1383.656650] li===> vi2_channel_start_streaming 2222222222
[ 1383.656652] li===> vi2_channel_start_streaming 444444444
[ 1383.656657] li===> vi2_channel_start_streaming 55555555
[ 1383.656860] li===> vi2_channel_start_streaming 6666666666
[ 1383.656863] li===> vi2_channel_start_streaming 888888888888
[ 1383.656881] li===> vb2_core_dqbuf type:1 memory:1 index:0
[ 1383.656910] li===> tegra_channel_kthread_capture_start
[ 1383.656914] li===> tegra_channel_capture_frame chan->low_latency:0
[ 1383.656918] li===> tegra_channel_capture_frame_single_thread: bfirst_fstart:0
[ 1383.656921] li===> tegra_channel_enable_stream: 1111111111
[ 1383.658013] li===> 1111 tegra_csi_s_stream enable:1
[ 1383.658016] li===> 2222 tegra_csi_s_stream
[ 1383.658018] li===> 3333 tegra_csi_s_stream
[ 1383.658020] li===> 4444 tegra_csi_s_stream
[ 1383.658022] li===> tegra_csi_s_stream valid_ports:1
[ 1383.658025] li===> tegra_csi_start_streaming port_idx:0
[ 1383.658031] vi 54080000.vi: settle time reading from props
[ 1383.658035] vi 54080000.vi: discontinuous_clk = 0 reading from props
[ 1383.658038] li===> cil_settletime:0 csi_port : 4 csi_lanes:4
[ 1383.730798] ===ar0521_reg_30fps_init OK!===
[ 1383.730808] ar0521 6-0036: li===> tegracam_init_ctrl_ranges_by_mode: modeidx:0 num_modes:2
[ 1383.731022] li===> tegra_channel_enable_stream: set_stream ret:0
[ 1383.731030] li===> tegra_channel_enable_stream: write_blobs ret:0
[ 1383.731034] li===> tegra_channel_capture_frame_single_thread: 222222222222
[ 1383.784217] li===> TEGRA_CSI_PIXEL_PARSER_STATUS err:0 val:0
[ 1383.784226] li===> TEGRA_CSI_CIL_STATUS err:0 val:48
[ 1383.784231] li===> TEGRA_CSI_CILX_STATUS err:0 val:262209
[ 1383.784237] li===> tegra_channel_capture_frame chan->low_latency:0
[ 1383.784243] li===> tegra_channel_capture_frame_single_thread: bfirst_fstart:1
[ 1383.784247] li===> tegra_channel_capture_frame_single_thread: 222222222222
[ 1383.831077] li===> TEGRA_CSI_PIXEL_PARSER_STATUS err:0 val:0
[ 1383.831119] li===> TEGRA_CSI_CIL_STATUS err:0 val:0
[ 1383.831150] li===> TEGRA_CSI_CILX_STATUS err:0 val:0
[ 1383.831188] li===> tegra_channel_capture_frame chan->low_latency:0
[ 1383.831230] li===> tegra_channel_capture_frame_single_thread: bfirst_fstart:1
[ 1383.831264] li===> tegra_channel_capture_frame_single_thread: 222222222222
[ 1383.876568] li===> TEGRA_CSI_PIXEL_PARSER_STATUS err:0 val:0
[ 1383.876608] li===> TEGRA_CSI_CIL_STATUS err:0 val:0
[ 1383.876637] li===> TEGRA_CSI_CILX_STATUS err:0 val:0
[ 1383.876767] li===> tegra_channel_capture_frame chan->low_latency:0
[ 1383.876811] li===> tegra_channel_capture_frame_single_thread: bfirst_fstart:1
[ 1383.876842] li===> tegra_channel_capture_frame_single_thread: 222222222222
[ 1383.877198] li===> __fill_v4l2_buffer 2222222222222
[ 1383.877251] li===> dqbuf of buffer 0, with state 0
[ 1383.921827] li===> TEGRA_CSI_PIXEL_PARSER_STATUS err:0 val:0
[ 1383.921832] li===> TEGRA_CSI_CIL_STATUS err:0 val:0
[ 1383.921835] li===> TEGRA_CSI_CILX_STATUS err:0 val:0
[ 1383.922143] li===> __fill_v4l2_buffer 2222222222222
[ 1383.922173] li===> tegra_channel_capture_frame chan->low_latency:0
[ 1383.922179] li===> tegra_channel_capture_frame_single_thread: bfirst_fstart:1
[ 1383.922181] li===> tegra_channel_capture_frame_single_thread: 222222222222
[ 1383.922183] li===> vb2_ioctl_streamoff
[ 1383.967844] li===> TEGRA_CSI_PIXEL_PARSER_STATUS err:0 val:0
[ 1383.967873] li===> TEGRA_CSI_CIL_STATUS err:0 val:0
[ 1383.967894] li===> TEGRA_CSI_CILX_STATUS err:0 val:0
[ 1383.969035] li===> 1111 tegra_csi_s_stream enable:0
[ 1383.969039] li===> 2222 tegra_csi_s_stream
[ 1383.969043] li===> 3333 tegra_csi_s_stream
[ 1383.969046] li===> 4444 tegra_csi_s_stream
[ 1383.969049] li===> tegra_csi_s_stream valid_ports:1
[ 1384.110197] ar0521 6-0036: ar0521_power_off: power off
[ 1384.110441] ar0521 6-0036: camera_common_mclk_disable: disable MCLK

I can get raw image by this cmd.

1

hello y2zwei,

there’re two approaches to access the camera stream, VI mode (i.e. v4l2-ctl) and VI-bypass (i.e. nvarguscamerasrc) mode.
VI mode only enable powers to perform sensor operation, but VI-bypass mode depends-on the mostly signal configurations in the sensor device tree.
since you have two identical sensors, I would suggest you narrow down the issue by arrange hardware resources to probe the MIPI signaling.
thanks

Hi Jerry,
I used an oscilloscope to test the data and clock pins of csi2 and csi3, and they all have normal signals, when I use the v4l2 command to test.

1

hello y2zwei,

as I mentioned before, there’re two approaches to access the camera stream.
you’ll should probe the signaling while enable the stream with nvarguscamerasrc plugin.

BTW,
why you’re making duplicate replies continuously?

Hi Jerry,
The difference between rbpcv2_imx219_e and rbpcv2_imx219_c in the device tree is that rbpcv2_imx219_e is a child node of host1x, because its i2c is also a child node of host1x. But the two camera nodes in the device tree of imx219 are also child nodes of host1x. I don’t know if there is a problem here.

  1. the bpcv2_imx219_e can’t enable the stream with nvarguscamerasrc plugin.
  2. Sometimes it doesn’t have this icon

hello y2zwei,

so that’s why you need to monitor the MIPI signaling behavior.
you may tweak the sensor driver to disable shutdown functions for issue checking.


you may use the “Reply” below a post to show that icon;
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thanks

Hi Jerry,
I disable shutdown functions stop_streaming, power_off,camera_common_mclk_disable .
and test the data and clock pins of csi2 and csi3, and they all have normal signals.