I am trying to interface a cs4272 with the Orin Nano, however the Cs4272 requires 3 clock signals, MCLK, SCLK, and LRCK. The nano’s I2S interface, i believe, produces 2 out of the 3 clocks that i need (eg. SCLK and LRCK). Could i use an independent GPIO to generate the master clock signal and if so how would i do that?
Hi rogDesign,
Are you using the devkit or custom board for Orin Nano?
What’s the Jetpack version in use?
It seems you want to port a audio codec, have you requested the porting guide from your vendor for its usage?
Can a GPIO generate a clock signal?
Please use PIN7(AUD_MCLK) of 40-pin GPIO expansion header for MCLK.
Im using the devkit and Jetpack 6.2.
Yes i believe it is in the datasheet, given by the following:
“5.2.1 Recommended Power-Up Sequence - Access to Control Port Mode 1) When using the CS4272 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are stable. When using the CS4272 with internally generated MCLK, hold RST low until the power supply is stable. In this state, the Control Port is reset to its default settings. 2) Bring RST high. The device will remain in a low power state and the control port will be accessible. If internally generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from the release of RST. 3) Write 03h to register 07h within 10 ms following the release of RST. This sets the Control Port Enable (CPEN) and Power Down (PDN) bits, activating the Control Port and placing the part in power-down. When using the CS4272 with internally generated MCLK, it is necessary to wait 1 ms following the release of RST before initiating this Control Port write. 4) The desired register settings can be loaded while keeping the PDN bit set. 5) Clear the PDN bit to initiate the power-up sequence. This power-up sequence requires approximately 85 µS. 5.2.2 Master / Slave Mode Selection The CS4272 supports operation in either Master Mode or Slave Mode. In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and SCLK is equal to 64x Fs. In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recommended that SCLK be 64x Fs to maximize system performance. Configuration of clock ratios in each of these modes will be outlined in the Tables 8 and 9. In Control Port Mode the CS4272 will default to Slave Mode. The user may change this default setting by changing the status of the M/S bit in the Mode Control 1 register (01h).”
I will look into this, as i am new to using the Jetson Orin Nano.
You can also refer to Audio Setup and Development — NVIDIA Jetson Linux Developer Guide for details about porting audio codec on Jetson.
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