CAN Bus setup error on Auvidea Carrier Board - mttcan: unable to set CAN_CLK parent

Dear Jetson Community,

I am using a 3rd party carrier board for the AGX Xavier module: The X221-AI from

When trying to set up the can interface following this tutorial, I ran into the following error when executing

$ sudo modprobe mttcan

[ … ]
[ 155.924887] can: controller area network core (rev 20120528 abi 9)
[ 155.926356] NET: Registered protocol family 29
[ 160.256598] can: raw protocol (rev 20120528)
[ 164.745128] CAN device driver interface
[ 164.753593] mttcan c310000.mttcan: unable to set CAN_CLK parent
[ 164.775906] mttcan c310000.mttcan: probe failed
[ 164.780208] tegra-asoc: sound: ASoC: CODEC DAI rt5659-aif1 not registered
[ 164.780410] tegra-asoc: sound: snd_soc_register_card failed (-517)
[ 164.782149] mttcan c320000.mttcan: unable to set CAN_CLK parent
[ 164.803892] mttcan c320000.mttcan: probe failed
[ … ]

Searching the web and this forum, multiple users had similar issues:

So my error seems to be related to the clock settings for can0 & can1. What I learned from searching this forum is that these settings are configured in various device tree files. The manufacturer of the carrier board ships ready-to-flash files for Jetpack 4.6.:
After extracting the tar archive, I can run

$ sudo bash ./flashcmd.txt

to flash the Xavier. I have been trying to resolve the issue, but without much success. This is what I have tried:

These are my modified files (I modified p2888-a01.dtb instead of p2888-a04.dtb because the -a04.dtb did not seem to be used in the normal flashing process. There is no single line mentioning the -a04.dtb. Instead, the -a01.dtb is present in the flash logs.):
tegra194-a02-bpmp-p2888-a01.dtb (965.7 KB)
tegra194-p2888-0001-p2822-0000.dtb (285.4 KB)

  • Modify the same files trying to revert back to pll_c instead of pllaon

Both attempts seem to not have any effect - I always get the same return values from the following commands:

$ cat /proc/device-tree/mttcan@c310000/pll_source

$ xxd /proc/device-tree/mttcan@c310000/clocks
00000000: 0000 0004 0000 011c 0000 0004 0000 000a …
00000010: 0000 0004 0000 0009 0000 0004 0000 005e …^

$ sudo cat /sys/kernel/debug/bpmp/debug/clk/can1/parent

$ sudo cat /sys/kernel/debug/bpmp/debug/clk/can1/possible_parents
clk_32k osc pll_c

My question now is, am I missing something in the process of modifying the correct files?
What else can I do to try to fix the CAN Bus?

Thank you for reading :)

hello Granki,

may I know how you modify the device tree,
did you disassemble the binary to modify the values, or you’ve build the binary from sources?

please also check clock tree for clock parents. i.e. # cat /sys/kernel/debug/clk/clk_summary

you may see-also the developer guide, Changing the CAN parent clock on T194 platforms. are you able to update the CAN clock rates?

Hi Jerry,

I used the dtc tool to convert between .dtb and .dts:

$ dtc -I dtb -O dts tegra194-a02-bpmp-p2888-a01.dtb -o tegra194-a02-bpmp-p2888-a01.dts
$ dtc -I dtb -O dts tegra194-p2888-0001-p2822-0000.dtb -o tegra194-p2888-0001-p2822-0000.dts

…Then edit using gedit… and convert back:

$ dtc -I dts -O dtb tegra194-a02-bpmp-p2888-a01.dts -o tegra194-a02-bpmp-p2888-a01.dtb
$ dtc -I dts -O dtb tegra194-p2888-0001-p2822-0000.dts -o tegra194-p2888-0001-p2822-0000.dtb

The conversion does throw some warnings, please see the following files:
p2888-DTStoDTB.txt (62.3 KB)
bpmp-DTStoDTB.txt (222.2 KB)
bpmp-DTBtoDTS.txt (222.2 KB)
p2888-DTBtoDTS.txt (62.3 KB)

This is what I get from checking the clock parents:

$ cat /sys/kernel/debug/clk/clk_summary
clk_summary.txt (36.2 KB)

I have not yet touched the kernel sources. The carrier board manufacturer does provide their modified kernel sources, however. So building the binaries based on the sources may be another option for me.

Do you know where I can find the mttcan driver file that is referenced in your linked developer guide?

This is my flashlog, maybe it is of some use:
flashlog.txt (393.7 KB)

hello Granki,

please apply the modifications and update the kernel images.

you may access Jetson Linux Archive | NVIDIA Developer to enter the l4t release version, please download the same release version of [L4T Driver Package (BSP) Sources] to obtain the public sources.

please refer to developer guide for the steps, Building the NVIDIA Kernel.

after that,
please check /boot/extlinux/extlinux.conf, it’s LINUX entry to specify the kernel image, you should modify that and point to your compiled kernel image.

Jerry, thank you for guiding me in the right direction.

I can now access the can bus on my device.

I downloaded the manufacturer’s kernel sources and made the following modification:


clocks-init {
	compatible = "nvidia,clocks-config";
	status = "okay";
	disable {							// remove PLLAON clock from disabled clocks(fd)
		clocks =/* <&aon_clks TEGRA194_CLK_PLLAON>,*/
			<&bpmp_clks TEGRA194_CLK_CAN1>,
			<&bpmp_clks TEGRA194_CLK_CAN2>;

I believe this section caused the pllaon clock to be unavailable as parent clock for the can clocks. Other device tree files provided by the carrier board manufacturer seemed to be fine.

I then built the kernel according to the guide from steps 1. to 7. and then needed to edit the BPMPFW DTB (tegra194-a02-bpmp-p2888-a04.dtb) file in the /Linux_for_Tegra/bootloader/t186ref directory using the dtc tool according to the section To use PLLAON as clock source of the referenced guide.

Then I flashed the board and now I am able to use the CAN bus as expected, using pllaon as pll_source for mttcan.

I was wondering where the sources for tegra194-a02-bpmp-p2888-a04.dtb are located? Or is using the dtc tool to de-/recompile the only option here?

hello Granki,

this only deliver with binary file, we did out public the sources of bpmp.

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