Can I change the link order of the PCIe Lannes?

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
3

Hi,
Although it may not work with stock BSP, the following change can be used to enable it.
Also, please note that the below change hasn’t been tried/verified. So, please apply it as an experimental suggestion.

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 63c0e343d388..70b873c3203c 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -287,6 +287,16 @@
 #define PCIE2_RP_XP_REF_CPL_TO_CUSTOM_VALUE_MASK               (0x1FFFF << 14)
 #define PCIE2_RP_XP_REF_CPL_TO_CUSTOM_VALUE                    (0x1770 << 14)

+#define RP_VEND_XP_LANEMAP                                     0xFC0
+#define RP_VEND_XP_LANEMAP_SLOT_0                              GENMASK(3, 0)
+#define RP_VEND_XP_LANEMAP_SLOT_0_SHIFT                                0
+#define RP_VEND_XP_LANEMAP_SLOT_1                              GENMASK(7, 4)
+#define RP_VEND_XP_LANEMAP_SLOT_1_SHIFT                                4
+#define RP_VEND_XP_LANEMAP_SLOT_2                              GENMASK(11, 8)
+#define RP_VEND_XP_LANEMAP_SLOT_2_SHIFT                                8
+#define RP_VEND_XP_LANEMAP_SLOT_3                              GENMASK(15, 12)
+#define RP_VEND_XP_LANEMAP_SLOT_3_SHIFT                                12
+
 #define NV_PCIE2_RP_PRIV_MISC                                  0x00000FE0
 #define PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT                  (0xE << 0)
 #define PCIE2_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT                  (0xF << 0)
@@ -2223,6 +2233,15 @@ static void tegra_pcie_apply_sw_war(struct tegra_pcie_port *port,
                data |= RP_LINK_CONTROL_STATUS_2_TRGT_LNK_SPD_GEN1;
                rp_writel(port, data, RP_LINK_CONTROL_STATUS_2);

+               data = rp_readl(port, RP_VEND_XP_LANEMAP);
+               data &= ~RP_VEND_XP_LANEMAP_SLOT_0;
+               data |= (2 << RP_VEND_XP_LANEMAP_SLOT_1_SHIFT);
+               data &= ~RP_VEND_XP_LANEMAP_SLOT_1;
+               data |= (0 << RP_VEND_XP_LANEMAP_SLOT_1_SHIFT);
+               data &= ~RP_VEND_XP_LANEMAP_SLOT_2;
+               data |= (1 << RP_VEND_XP_LANEMAP_SLOT_2_SHIFT);
+               rp_writel(port, data, RP_VEND_XP_LANEMAP);
+
                /* disable interrupts for LTR messages */
                data = rp_readl(port, PCIE2_RP_L1SS_SPARE);
                data &= ~PCIE2_RP_L1SS_SPARE_LTR_MSG_INT_EN;
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