Hi there,
We have been making automotive devices for autonomous driving with Jetson ORIN AGX Module in it. Now we have a need to transfer large data realtime between the two autonomous devices, we want to connect the two ORIN AGXs in two devices by high speed transmission cable, and the cable length is up to 1.5meters. Can I extend the PCIE from one ORIN AGX to another ORIN AGX and how can I perform it? Please suggest adapted connectors and cable types as well if possible. Thank you.
Illustrations on Figure 7-5. PCIe Jetson AGX Orin RP to Jetson AGX Orin EP Connection Example in the design guide doc, it shows some isolators are required on “PEX_WAKE_N” “PEX_C5_RST_N” “PEX_C5_CLKREQ_N” “GPIO38”, can anyone tells what kind of isolator is to be used here? How do I connect the SRNS clocking to each SOC?
Regarding chip-to-chip communication over PICe, we don’t have a reference to recommend but it should be OK if a PCIe cable meets the insertion loss specified in the Jetson AGX Orin Design Guide.
We are checking internally regarding isolator between two Jetson AGX Orin Modules.
The isolator is to avoid back drive current when a Jetson AGX Orin module is on while the other side is off. You can consider to add a level shifter as an isolator.
Thank you for the reply.
Please also check below addtional questions,
How do I connect the SRNS/SRIS clock on each end of the PCIe RC/EP?
Does it require a common clock connecting from the PCIe RC to the PCIe EP?
There are different topologies such as RC-to-EP/RC-to-RC/EP-to-EP to achieve PCIe data transmission across two devices over high-speed cable, I am going to build it across two identical devices with same hardware design, which PCIE topology should I take? and whats the recommend PCIe connections for the AGX ORIN?
SRNS uses internal PLL as its clock source. Both RP and EP work in async.
Please find the notes below from Figure 7-5 in the Jetson AGX Orin Design Guide for your reference.
Hi egu,
Thanks for the reply.
I want to use the SRNS clocking seperatly instead of the common clocking from the RC side to the EP side, please help to check the clock connections on both the Root Complex and the Endpoit of the AGX ORINs. Which PIN of the AGX ORIN should be connected to the SRNS1 clock when it works at Root Complex mode? and which PIN of the AGX ORIN should be connected to the SRNS2 clock when it works at Endpoint mode?
There is no additional clock is required but the internal PLL will provide clocks to the PCIe controller for SRNS.
Do you design your own carrier board ? What about the cable ? off-the-shelf or custom cable ?
Yes I am designing a custom carrier board, and have checked the Figure 7-5 in the design guide. To connect the PCIe signals to an external socket I need to understand what signals of the PCIe are required to connect the external socket on either of the RC and the EP. Can you help to clarify the doubts?
As regard to the PCIe cable, I am going to take a passive cable with only x4 lanes of differential signal data, but for the low speed signals like WAKE_N, CLKREQ_N, RST_N, GPIO38 can be left unconnected on local PCB, the CLK_P/N can be SRNS clock on local PCB. Could you advise me on these?
Figure 7-5 is required signals.
One additional question, in case of an PCIe AEC cable is adopted instead of a passive cable, what signals of the PCIe should be routed to the AEC cable from the ORIN Module?
Hello,
I need your confirmation on what is the PIN on the AGX ORIN to be connected the SRNS clock when AGX ORIN Module working as Root Complex (RC)? the PEX_CLK5_N/P or the UPHY_CLK0_N/P ?
SRNS uses an internal PLL so it does not need an external clock like 100MHz.
Please refer to the Figure 7-5 for chip to chip communication over PCIe.
Hello egu,
I am wondering if the SRNS clock is already built in the AGX ORIN?
And how do I deal with the PEX_CLK5_N/P pins and the UPHY_CLK0_N/P pins if they are not used in SRNS mode, can I just leave them unconnected(open)?
Please refer to the Jetson AGX Orin Series Design Guide (including AGX Orin Industrial) for the JAO module to module communication.
Hello EricGggg,
I cannot find the content in the “Jetson AGX Orin Series Module Design Guide v1.81” as you say, can you let me know what is the section of it?
For PCIe, please refer to the Chapter 7.2.
Figure 7-5 is the connection example for JAO to JAO communication over PCIe.
