Can i control LCD1_BKLT_PWM?

hi

BSP version is R28.1

/sys/class/pwm/pwmchip0 --> LCD0_BKLT_PWM --> OK
/sys/class/pwm/pwmchip1 --> N/A
/sys/class/pwm/pwmchip2 --> LCD1_BKLT_PWM --> Not OK
/sys/class/pwm/pwmchip3 --> FAN_PWM --> OK

echo 0 | sudo tee -a /sys/class/pwm/pwmchip[port]/export
echo $period | sudo tee -a /sys/class/pwm/pwmchip[port]/pwm0/period
echo $duty | sudo tee -a /sys/class/pwm/pwmchip[port]/pwm0/duty_cycle
echo 1 | sudo tee -a /sys/class/pwm/pwmchip[port]/pwm0/enable

Can i control LCD1_BKLT_PWM ?

Hi walterkim,
Yes, please try to use above command to control PWM.

Refer to kernel documentation https://www.kernel.org/doc/Documentation/pwm.txt for information related to
sysfs node of pwm controllers that comes up on enabling pwm.
Now to configure the pwm with 20us period and 50% duty cycle through sysfs, do the following:

cd /sys/class/pwm/pwmchip0

echo 0 > export

cd pwm0

echo 20000 > period (20us is the total time period of the pulse)

echo 10000 > duty_cycle (50% duty cycle)

echo 1 > enable

Now if we probe the pwm lines we can see pwm pulse of period 20us and 50% duty cycle.

hi WayneWWW

I tested LCD1_BKLT_PWM. but there is no output. So I asked.

BSP version is R28.1(Jetson Tx2)

Can i control LCD1_BKLT_PWM ?

Hi walterkim,

Could you try to control GPIO pin U5?

hi WayneWWW

i tested U5 gpio.
it was controlled high/low.
but PWM was not controlled.

Can i control LCD1_BKLT_PWM ?

Hi walterkim,

Which device tree are you using?
Do you have similar configuration in device tree as below?

backlight {
                              status = "okay";
                              panel-s-wuxga-8-0-bl {
                                             pwms = <&tegra_pwm1 0 40161>;
                              };
                              panel-s-wqxga-10-1-bl {
                                             pwms = <&tegra_pwm1 0 1000000>;
                              };
                panel-s-edp-uhdtv-15-6-bl {
                        pwms = <&tegra_pwm3 0 5000000>;
                };
                              panel-a-edp-1080p-14-0-bl {
                                             pwms = <&tegra_pwm1 0 1000000>;
                              };
               };
 
               tegra_pwm1: pwm@3280000 {
                              status = "okay";
               };
 
               tegra_pwm2: pwm@3290000 {
                              status = "okay";
               };
 
               tegra_pwm3: pwm@32a0000 {
                              status = "okay";
               };
 
               tegra_pwm4: pwm@c340000 {
                              status = "okay";
               };

hi WayneWWW

yes!

It is the same as mine.

Can i control LCD1_BKLT_PWM ?

When you set gpio pin U5 to high, is there any output from that pin?
If yes, when you set this as steps in #3, is there any output?

hi WayneWWW

I tested below. PWM is not working.
Can i control LCD1_BKLT_PWM ?

//GPIO HIGH
echo 269 | sudo tee -a /sys/class/gpio/export 
echo "out" | sudo tee -a /sys/class/gpio/gpio269/direction
echo "1" | sudo tee -a /sys/class/gpio/gpio269/value   <<<<<<<<<<<<<<<<< my scope displayed high

//PWM Enable
echo 0 | sudo tee -a /sys/class/pwm/pwmchip2/export
echo 33333333 | sudo tee -a /sys/class/pwm/pwmchip2/pwm0/period
echo 16666666 | sudo tee -a /sys/class/pwm/pwmchip2/pwm0/duty_cycle
echo 1 | sudo tee -a /sys/class/pwm/pwmchip2/pwm0/enable   <<<<<<<<<<<<<<< not output

HI walterkim,

Sorry for the late reply.

Could you share the value of.

root@tegra-ubuntu:/sys/kernel/debug# cat tegra-gpio-on
root@tegra-ubuntu:/sys/class/pwm/pwmchip2/pwm0# cat /sys/kernel/debug/tegra_pinctrl_reg

Also, Do you use custom pinmux or directly flashed by jetpack?

HI walterkim,

Please update previous question. Thanks.

hi WayeWWW

check please below

thank you

root@tegra-ubuntu:/sys/kernel/debug# cat tegra-gpio-on
Port:Pin:ENB DBC IN OUT_CTRL OUT_VAL INT_CLR
S:0 0x0 0x0 0x0 0x1 0x0 0x0
S:1 0x0 0x0 0x0 0x1 0x0 0x0
S:2 0x0 0x0 0x0 0x1 0x0 0x0
S:3 0x4d 0x5 0x1 0x0 0x0 0x0
S:4 0x0 0x0 0x0 0x1 0x0 0x0
U:0 0x0 0x0 0x0 0x1 0x0 0x0
U:1 0x0 0x0 0x0 0x1 0x0 0x0
U:2 0x0 0x0 0x0 0x1 0x0 0x0
U:3 0x4d 0x5 0x1 0x0 0x0 0x0
U:4 0x0 0x0 0x0 0x1 0x0 0x0
U:5 0x0 0x0 0x0 0x1 0x0 0x0
V:0 0x45 0x0 0x1 0x1 0x0 0x0
V:1 0x0 0x0 0x0 0x1 0x0 0x0
V:2 0x0 0x0 0x0 0x1 0x0 0x0
V:3 0x0 0x0 0x0 0x1 0x0 0x0
V:4 0x0 0x0 0x0 0x1 0x0 0x0
V:5 0x3 0x0 0x0 0x0 0x0 0x0
V:6 0x0 0x0 0x0 0x1 0x0 0x0
V:7 0x0 0x0 0x0 0x1 0x0 0x0
W:0 0x0 0x0 0x0 0x1 0x0 0x0
W:1 0x0 0x0 0x0 0x1 0x0 0x0
W:2 0x0 0x0 0x0 0x1 0x0 0x0
W:3 0x0 0x0 0x0 0x1 0x0 0x0
W:4 0x0 0x0 0x0 0x1 0x0 0x0
W:5 0x0 0x0 0x0 0x1 0x0 0x0
W:6 0x0 0x0 0x0 0x1 0x0 0x0
W:7 0x0 0x0 0x0 0x1 0x0 0x0
Z:0 0x0 0x0 0x0 0x1 0x0 0x0
Z:1 0x0 0x0 0x0 0x1 0x0 0x0
Z:2 0x0 0x0 0x0 0x1 0x0 0x0
Z:3 0x0 0x0 0x0 0x1 0x0 0x0
AA:0 0x0 0x0 0x0 0x1 0x0 0x0
AA:1 0x0 0x0 0x0 0x1 0x0 0x0
AA:2 0x1 0x0 0x0 0x1 0x0 0x0
AA:3 0x1 0x0 0x1 0x1 0x0 0x0
AA:4 0x1 0x0 0x1 0x1 0x0 0x0
AA:5 0x1 0x0 0x1 0x1 0x0 0x0
AA:6 0x3 0x0 0x0 0x0 0x0 0x0
AA:7 0x1 0x0 0x1 0x1 0x0 0x0
EE:0 0x0 0x0 0x0 0x1 0x0 0x0
EE:1 0x0 0x0 0x0 0x1 0x0 0x0
EE:2 0x0 0x0 0x0 0x1 0x0 0x0
FF:0 0x4d 0x5 0x1 0x1 0x0 0x0
FF:1 0x4d 0x5 0x1 0x1 0x0 0x0
FF:2 0x1 0x0 0x1 0x1 0x0 0x0
FF:3 0x55 0x0 0x0 0x1 0x0 0x0
FF:4 0x59 0x0 0x0 0x1 0x0 0x0

root@tegra-ubuntu:/sys/kernel/debug# cat /sys/kernel/debug/tegra_pinctrl_reg
Bank: 1 Reg: 0x0c302000 Val: 0x00000400 -> touch_clk_pee2
Bank: 1 Reg: 0x0c302008 Val: 0x00000458 -> uart3_cts_pw5
Bank: 1 Reg: 0x0c302010 Val: 0x00000400 -> uart3_rts_pw4
Bank: 1 Reg: 0x0c302018 Val: 0x00000458 -> uart3_rx_pw3
Bank: 1 Reg: 0x0c302020 Val: 0x00000400 -> uart3_tx_pw2
Bank: 1 Reg: 0x0c302028 Val: 0x00001440 -> gen8_i2c_sda_pw1
Bank: 1 Reg: 0x0c302030 Val: 0x00001440 -> gen8_i2c_scl_pw0
Bank: 1 Reg: 0x0c302038 Val: 0x00000448 -> uart7_rx_pw7
Bank: 1 Reg: 0x0c302040 Val: 0x00000448 -> uart7_tx_pw6
Bank: 1 Reg: 0x0c302048 Val: 0x00000058 -> gpio_sen0_pv0
Bank: 1 Reg: 0x0c302050 Val: 0x00000444 -> gpio_sen1_pv1
Bank: 1 Reg: 0x0c302058 Val: 0x00000444 -> gpio_sen2_pv2
Bank: 1 Reg: 0x0c302060 Val: 0x00000444 -> gpio_sen3_pv3
Bank: 1 Reg: 0x0c302068 Val: 0x00000448 -> gpio_sen4_pv4
Bank: 1 Reg: 0x0c302070 Val: 0x00000000 -> gpio_sen5_pv5
Bank: 1 Reg: 0x0c302078 Val: 0x00000401 -> gpio_sen6_pv6
Bank: 1 Reg: 0x0c302080 Val: 0x00000401 -> gpio_sen7_pv7
Bank: 1 Reg: 0x0c302088 Val: 0x00001441 -> gpio_sen8_pee0
Bank: 1 Reg: 0x0c302090 Val: 0x00001441 -> gpio_sen9_pee1
Bank: 1 Reg: 0x0c303000 Val: 0x00000050 -> can_gpio7_paa7
Bank: 1 Reg: 0x0c303008 Val: 0x00000400 -> can1_dout_pz0
Bank: 1 Reg: 0x0c303010 Val: 0x00000458 -> can1_din_pz1
Bank: 1 Reg: 0x0c303018 Val: 0x00000400 -> can0_dout_pz2
Bank: 1 Reg: 0x0c303020 Val: 0x00000458 -> can0_din_pz3
Bank: 1 Reg: 0x0c303028 Val: 0x00006452 -> can_gpio0_paa0
Bank: 1 Reg: 0x0c303030 Val: 0x00006402 -> can_gpio1_paa1
Bank: 1 Reg: 0x0c303038 Val: 0x00000059 -> can_gpio2_paa2
Bank: 1 Reg: 0x0c303040 Val: 0x00000040 -> can_gpio3_paa3
Bank: 1 Reg: 0x0c303048 Val: 0x00000058 -> can_gpio4_paa4
Bank: 1 Reg: 0x0c303050 Val: 0x00000040 -> can_gpio5_paa5
Bank: 1 Reg: 0x0c303058 Val: 0x00000000 -> can_gpio6_paa6
Bank: 0 Reg: 0x02431000 Val: 0x00000401 -> gpio_aud3_pk0
Bank: 0 Reg: 0x02431008 Val: 0x00000401 -> gpio_aud2_pj7
Bank: 0 Reg: 0x02431010 Val: 0x00000000 -> gpio_aud1_pj6
Bank: 0 Reg: 0x02431018 Val: 0x00000058 -> gpio_aud0_pj5
Bank: 0 Reg: 0x02431020 Val: 0x00000400 -> aud_mclk_pj4
Bank: 0 Reg: 0x02431028 Val: 0x00000440 -> dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000450 -> dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000440 -> dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000440 -> dap1_sclk_pj0
Bank: 0 Reg: 0x02432000 Val: 0x00006441 -> dmic1_clk_pm1
Bank: 0 Reg: 0x02432008 Val: 0x00006451 -> dmic1_dat_pm0
Bank: 0 Reg: 0x02432010 Val: 0x00006441 -> dmic2_dat_pm2
Bank: 0 Reg: 0x02432018 Val: 0x00006441 -> dmic2_clk_pm3
Bank: 0 Reg: 0x02432020 Val: 0x00006002 -> dmic4_dat_pm4
Bank: 0 Reg: 0x02432028 Val: 0x0000605a -> dmic4_clk_pm5
Bank: 0 Reg: 0x02432030 Val: 0x00006440 -> dap4_fs_pcc3
Bank: 0 Reg: 0x02432038 Val: 0x00006450 -> dap4_din_pcc2
Bank: 0 Reg: 0x02432040 Val: 0x00006440 -> dap4_dout_pcc1
Bank: 0 Reg: 0x02432048 Val: 0x00006440 -> dap4_sclk_pcc0
Bank: 0 Reg: 0x02430000 Val: 0x00000400 -> extperiph2_clk_po1
Bank: 0 Reg: 0x02430008 Val: 0x00000400 -> extperiph1_clk_po0
Bank: 0 Reg: 0x02430010 Val: 0x00001440 -> cam_i2c_sda_po3
Bank: 0 Reg: 0x02430018 Val: 0x00001440 -> cam_i2c_scl_po2
Bank: 0 Reg: 0x02430020 Val: 0x00000001 -> gpio_cam1_pn0
Bank: 0 Reg: 0x02430028 Val: 0x00000401 -> gpio_cam2_pn1
Bank: 0 Reg: 0x02430030 Val: 0x00000002 -> gpio_cam3_pn2
Bank: 0 Reg: 0x02430038 Val: 0x00000445 -> gpio_cam4_pn3
Bank: 0 Reg: 0x02430040 Val: 0x00000445 -> gpio_cam5_pn4
Bank: 0 Reg: 0x02430048 Val: 0x00000445 -> gpio_cam6_pn5
Bank: 0 Reg: 0x02430050 Val: 0x00000449 -> gpio_cam7_pn6
Bank: 0 Reg: 0x02434000 Val: 0x00000450 -> dap2_din_pc3
Bank: 0 Reg: 0x02434008 Val: 0x00000440 -> dap2_dout_pc2
Bank: 0 Reg: 0x02434010 Val: 0x00000440 -> dap2_fs_pc4
Bank: 0 Reg: 0x02434018 Val: 0x00000440 -> dap2_sclk_pc1
Bank: 0 Reg: 0x02434020 Val: 0x00000458 -> uart4_cts_pb3
Bank: 0 Reg: 0x02434028 Val: 0x00000400 -> uart4_rts_pb2
Bank: 0 Reg: 0x02434030 Val: 0x00000458 -> uart4_rx_pb1
Bank: 0 Reg: 0x02434038 Val: 0x00000400 -> uart4_tx_pb0
Bank: 0 Reg: 0x02434040 Val: 0x00000048 -> gpio_wan4_pc0
Bank: 0 Reg: 0x02434048 Val: 0x00000000 -> gpio_wan3_pb6
Bank: 0 Reg: 0x02434050 Val: 0x00000048 -> gpio_wan2_pb5
Bank: 0 Reg: 0x02434058 Val: 0x00000000 -> gpio_wan1_pb4
Bank: 0 Reg: 0x02434060 Val: 0x00001460 -> gen1_i2c_scl_pc5
Bank: 0 Reg: 0x02434068 Val: 0x00001460 -> gen1_i2c_sda_pc6
Bank: 0 Reg: 0x02435000 Val: 0x00000401 -> uart1_cts_pt3
Bank: 0 Reg: 0x02435008 Val: 0x00000401 -> uart1_rts_pt2
Bank: 0 Reg: 0x02435010 Val: 0x00000458 -> uart1_rx_pt1
Bank: 0 Reg: 0x02435018 Val: 0x00000400 -> uart1_tx_pt0
Bank: 0 Reg: 0x02435028 Val: 0x00022448 -> directdc1_out3_pq5
Bank: 0 Reg: 0x02435030 Val: 0x00022448 -> directdc1_out2_pq4
Bank: 0 Reg: 0x02435038 Val: 0x00022448 -> directdc1_out1_pq3
Bank: 0 Reg: 0x02435040 Val: 0x00022448 -> directdc1_out0_pq2
Bank: 0 Reg: 0x02435048 Val: 0x00022444 -> directdc1_in_pq1
Bank: 0 Reg: 0x02435050 Val: 0x00022448 -> directdc1_clk_pq0
Bank: 0 Reg: 0x02435058 Val: 0x00002000 -> directdc_comp
Bank: 0 Reg: 0x02433000 Val: 0x00006446 -> gpio_pq0_pi0
Bank: 0 Reg: 0x02433008 Val: 0x00006446 -> gpio_pq1_pi1
Bank: 0 Reg: 0x02433010 Val: 0x00006456 -> gpio_pq2_pi2
Bank: 0 Reg: 0x02433018 Val: 0x00006446 -> gpio_pq3_pi3
Bank: 0 Reg: 0x02433020 Val: 0x00004058 -> gpio_pq4_pi4
Bank: 0 Reg: 0x02433028 Val: 0x00004000 -> gpio_pq5_pi5
Bank: 0 Reg: 0x02433030 Val: 0x00004048 -> gpio_pq6_pi6
Bank: 0 Reg: 0x02433038 Val: 0x00004044 -> gpio_pq7_pi7
Bank: 0 Reg: 0x02440000 Val: 0x00000158 -> gpio_edp2_pp5
Bank: 0 Reg: 0x02440008 Val: 0x00000000 -> gpio_edp3_pp6
Bank: 0 Reg: 0x02440010 Val: 0x00000040 -> gpio_edp0_pp3
Bank: 0 Reg: 0x02440018 Val: 0x00000058 -> gpio_edp1_pp4
Bank: 0 Reg: 0x02440020 Val: 0x00000550 -> dp_aux_ch0_hpd_pp0
Bank: 0 Reg: 0x02440028 Val: 0x00000151 -> dp_aux_ch1_hpd_pp1
Bank: 0 Reg: 0x02440030 Val: 0x00000560 -> hdmi_cec_pp2
Bank: 0 Reg: 0x02437000 Val: 0x00000560 -> pex_l2_clkreq_n_pa6
Bank: 0 Reg: 0x02437008 Val: 0x00000570 -> pex_wake_n_pa2
Bank: 0 Reg: 0x02437010 Val: 0x00000560 -> pex_l1_clkreq_n_pa4
Bank: 0 Reg: 0x02437018 Val: 0x00000520 -> pex_l1_rst_n_pa3
Bank: 0 Reg: 0x02437020 Val: 0x00000560 -> pex_l0_clkreq_n_pa1
Bank: 0 Reg: 0x02437028 Val: 0x00000520 -> pex_l0_rst_n_pa0
Bank: 0 Reg: 0x02437030 Val: 0x00000520 -> pex_l2_rst_n_pa5
Bank: 0 Reg: 0x02438000 Val: 0x00002460 -> sdmmc1_clk_pd0
Bank: 0 Reg: 0x02438008 Val: 0x00002448 -> sdmmc1_cmd_pd1
Bank: 0 Reg: 0x02438010 Val: 0x00000000 -> sdmmc1_comp
Bank: 0 Reg: 0x02438014 Val: 0x00002448 -> sdmmc1_dat3_pd5
Bank: 0 Reg: 0x0243801c Val: 0x00002448 -> sdmmc1_dat2_pd4
Bank: 0 Reg: 0x02438024 Val: 0x00002448 -> sdmmc1_dat1_pd3
Bank: 0 Reg: 0x0243802c Val: 0x00002448 -> sdmmc1_dat0_pd2
Bank: 0 Reg: 0x02439000 Val: 0x00002400 -> eqos_td3_pe4
Bank: 0 Reg: 0x02439008 Val: 0x00002400 -> eqos_td2_pe3
Bank: 0 Reg: 0x02439010 Val: 0x00002400 -> eqos_td1_pe2
Bank: 0 Reg: 0x02439018 Val: 0x00002400 -> eqos_td0_pe1
Bank: 0 Reg: 0x02439020 Val: 0x00002450 -> eqos_rd3_pf1
Bank: 0 Reg: 0x02439028 Val: 0x00002450 -> eqos_rd2_pf0
Bank: 0 Reg: 0x02439030 Val: 0x00002450 -> eqos_rd1_pe7
Bank: 0 Reg: 0x02439038 Val: 0x00002448 -> eqos_mdio_pf4
Bank: 0 Reg: 0x02439040 Val: 0x00002450 -> eqos_rd0_pe6
Bank: 0 Reg: 0x02439048 Val: 0x00002400 -> eqos_mdc_pf5
Bank: 0 Reg: 0x02439050 Val: 0x00000000 -> eqos_comp
Bank: 0 Reg: 0x02439054 Val: 0x00002400 -> eqos_txc_pe0
Bank: 0 Reg: 0x0243905c Val: 0x00002450 -> eqos_rxc_pf3
Bank: 0 Reg: 0x02439064 Val: 0x00002400 -> eqos_tx_ctl_pe5
Bank: 0 Reg: 0x0243906c Val: 0x00002450 -> eqos_rx_ctl_pf2
Bank: 0 Reg: 0x0243a000 Val: 0x00002448 -> sdmmc3_dat3_pg5
Bank: 0 Reg: 0x0243a008 Val: 0x00002448 -> sdmmc3_dat2_pg4
Bank: 0 Reg: 0x0243a010 Val: 0x00002448 -> sdmmc3_dat1_pg3
Bank: 0 Reg: 0x0243a018 Val: 0x00002448 -> sdmmc3_dat0_pg2
Bank: 0 Reg: 0x0243a020 Val: 0x00000000 -> sdmmc3_comp
Bank: 0 Reg: 0x0243a024 Val: 0x00002448 -> sdmmc3_cmd_pg1
Bank: 0 Reg: 0x0243a02c Val: 0x00002460 -> sdmmc3_clk_pg0
Bank: 0 Reg: 0x02436004 Val: 0x00002060 -> sdmmc4_clk
Bank: 0 Reg: 0x02436008 Val: 0x00002048 -> sdmmc4_cmd
Bank: 0 Reg: 0x0243600c Val: 0x00002040 -> sdmmc4_dqs
Bank: 0 Reg: 0x02436010 Val: 0x00002048 -> sdmmc4_dat7
Bank: 0 Reg: 0x02436014 Val: 0x00002048 -> sdmmc4_dat6
Bank: 0 Reg: 0x02436018 Val: 0x00002048 -> sdmmc4_dat5
Bank: 0 Reg: 0x0243601c Val: 0x00002048 -> sdmmc4_dat4
Bank: 0 Reg: 0x02436020 Val: 0x00002048 -> sdmmc4_dat3
Bank: 0 Reg: 0x02436024 Val: 0x00002048 -> sdmmc4_dat2
Bank: 0 Reg: 0x02436028 Val: 0x00002048 -> sdmmc4_dat1
Bank: 0 Reg: 0x0243602c Val: 0x00002048 -> sdmmc4_dat0
Bank: 0 Reg: 0x0243b000 Val: 0x00000001 -> qspi_io3_pr4
Bank: 0 Reg: 0x0243b008 Val: 0x00000001 -> qspi_io2_pr3
Bank: 0 Reg: 0x0243b010 Val: 0x00000001 -> qspi_io1_pr2
Bank: 0 Reg: 0x0243b018 Val: 0x00000001 -> qspi_io0_pr1
Bank: 0 Reg: 0x0243b020 Val: 0x00000001 -> qspi_sck_pr0
Bank: 0 Reg: 0x0243b028 Val: 0x00000059 -> qspi_cs_n_pr5
Bank: 0 Reg: 0x0243b030 Val: 0x00002000 -> qspi_comp
Bank: 1 Reg: 0x0c301000 Val: 0x00000058 -> gpio_sw1_pff1
Bank: 1 Reg: 0x0c301008 Val: 0x00000058 -> gpio_sw2_pff2
Bank: 1 Reg: 0x0c301010 Val: 0x00000058 -> gpio_sw3_pff3
Bank: 1 Reg: 0x0c301018 Val: 0x00000058 -> gpio_sw4_pff4
Bank: 1 Reg: 0x0c301020 Val: 0x00000040 -> shutdown
Bank: 1 Reg: 0x0c301028 Val: 0x00000040 -> pmu_int
Bank: 1 Reg: 0x0c301030 Val: 0x00000041 -> safe_state_ps3
Bank: 1 Reg: 0x0c301038 Val: 0x00000458 -> vcomp_alert_ps4
Bank: 1 Reg: 0x0c301040 Val: 0x00000040 -> soc_pwr_req
Bank: 1 Reg: 0x0c301048 Val: 0x00000458 -> batt_oc_ps2
Bank: 1 Reg: 0x0c301050 Val: 0x00001040 -> clk_32k_in
Bank: 1 Reg: 0x0c301058 Val: 0x00000058 -> power_on_pff0
Bank: 1 Reg: 0x0c301060 Val: 0x00001440 -> pwr_i2c_scl_ps0
Bank: 1 Reg: 0x0c301068 Val: 0x00001440 -> pwr_i2c_sda_ps1
Bank: 1 Reg: 0x0c301080 Val: 0x00000401 -> gpio_dis0_pu0
Bank: 1 Reg: 0x0c301088 Val: 0x00000456 -> gpio_dis1_pu1
Bank: 1 Reg: 0x0c301090 Val: 0x00000402 -> gpio_dis2_pu2
Bank: 1 Reg: 0x0c301098 Val: 0x00000040 -> gpio_dis3_pu3
Bank: 1 Reg: 0x0c3010a0 Val: 0x00000402 -> gpio_dis4_pu4
Bank: 1 Reg: 0x0c3010a8 Val: 0x00000411 -> gpio_dis5_pu5
Bank: 0 Reg: 0x0243d000 Val: 0x0000044a -> gpio_wan8_ph3
Bank: 0 Reg: 0x0243d008 Val: 0x00000446 -> gpio_wan7_ph2
Bank: 0 Reg: 0x0243d010 Val: 0x00000446 -> gpio_wan6_ph1
Bank: 0 Reg: 0x0243d018 Val: 0x00000446 -> gpio_wan5_ph0
Bank: 0 Reg: 0x0243d020 Val: 0x00000400 -> uart2_tx_px0
Bank: 0 Reg: 0x0243d028 Val: 0x00000458 -> uart2_rx_px1
Bank: 0 Reg: 0x0243d030 Val: 0x00000400 -> uart2_rts_px2
Bank: 0 Reg: 0x0243d038 Val: 0x00000458 -> uart2_cts_px3
Bank: 0 Reg: 0x0243d040 Val: 0x00000402 -> uart5_rx_px5
Bank: 0 Reg: 0x0243d048 Val: 0x00000452 -> uart5_tx_px4
Bank: 0 Reg: 0x0243d050 Val: 0x00000002 -> uart5_rts_px6
Bank: 0 Reg: 0x0243d058 Val: 0x0000005a -> uart5_cts_px7
Bank: 0 Reg: 0x0243d060 Val: 0x00000058 -> gpio_mdm1_py0
Bank: 0 Reg: 0x0243d068 Val: 0x00000058 -> gpio_mdm2_py1
Bank: 0 Reg: 0x0243d070 Val: 0x00000058 -> gpio_mdm3_py2
Bank: 0 Reg: 0x0243d078 Val: 0x00000409 -> gpio_mdm4_py3
Bank: 0 Reg: 0x0243d080 Val: 0x00000000 -> gpio_mdm5_py4
Bank: 0 Reg: 0x0243d088 Val: 0x00000059 -> gpio_mdm6_py5
Bank: 0 Reg: 0x0243d090 Val: 0x00000058 -> gpio_mdm7_py6
Bank: 0 Reg: 0x0243d098 Val: 0x00000000 -> bcpu_pwr_req_ph4
Bank: 0 Reg: 0x0243d0a0 Val: 0x00000000 -> mcpu_pwr_req_ph5
Bank: 0 Reg: 0x0243d0a8 Val: 0x00000000 -> gpu_pwr_req_ph6
Bank: 0 Reg: 0x0243d0b0 Val: 0x00001440 -> gen7_i2c_scl_pl0
Bank: 0 Reg: 0x0243d0b8 Val: 0x00001440 -> gen7_i2c_sda_pl1
Bank: 0 Reg: 0x0243d0c0 Val: 0x00001440 -> gen9_i2c_sda_pl3
Bank: 0 Reg: 0x0243d0c8 Val: 0x00001440 -> gen9_i2c_scl_pl2
Bank: 0 Reg: 0x0243d0d0 Val: 0x00000460 -> usb_vbus_en0_pl4
Bank: 0 Reg: 0x0243d0d8 Val: 0x00000470 -> usb_vbus_en1_pl5
Bank: 0 Reg: 0x0243d0e0 Val: 0x00000400 -> gp_pwm7_pl7
Bank: 0 Reg: 0x0243d0e8 Val: 0x00000400 -> gp_pwm6_pl6
Bank: 0 Reg: 0x02441000 Val: 0x00022001 -> ufs0_rst_pbb1
Bank: 0 Reg: 0x02441008 Val: 0x00022001 -> ufs0_ref_clk_pbb0
Bank: 1 Reg: 0x0c302004 Val: 0x00000000 -> drive_touch_clk
Bank: 1 Reg: 0x0c30200c Val: 0x00606000 -> drive_uart3_cts
Bank: 1 Reg: 0x0c302014 Val: 0x00606000 -> drive_uart3_rts
Bank: 1 Reg: 0x0c30201c Val: 0x00606000 -> drive_uart3_rx
Bank: 1 Reg: 0x0c302024 Val: 0x00606000 -> drive_uart3_tx
Bank: 1 Reg: 0x0c30202c Val: 0x0001f000 -> drive_gen8_i2c_sda
Bank: 1 Reg: 0x0c302034 Val: 0x0001f000 -> drive_gen8_i2c_scl
Bank: 1 Reg: 0x0c30203c Val: 0x00606000 -> drive_uart7_rx
Bank: 1 Reg: 0x0c302044 Val: 0x00606000 -> drive_uart7_tx
Bank: 1 Reg: 0x0c30204c Val: 0x00000000 -> drive_gpio_sen0
Bank: 1 Reg: 0x0c302054 Val: 0x00000000 -> drive_gpio_sen1
Bank: 1 Reg: 0x0c30205c Val: 0x00000000 -> drive_gpio_sen2
Bank: 1 Reg: 0x0c302064 Val: 0x00000000 -> drive_gpio_sen3
Bank: 1 Reg: 0x0c30206c Val: 0x00000000 -> drive_gpio_sen4
Bank: 1 Reg: 0x0c302074 Val: 0x00000000 -> drive_gpio_sen5
Bank: 1 Reg: 0x0c30207c Val: 0x00000000 -> drive_gpio_sen6
Bank: 1 Reg: 0x0c302084 Val: 0x00000000 -> drive_gpio_sen7
Bank: 1 Reg: 0x0c30208c Val: 0x0001f000 -> drive_gpio_sen8
Bank: 1 Reg: 0x0c302094 Val: 0x0001f000 -> drive_gpio_sen9
Bank: 1 Reg: 0x0c303004 Val: 0x00000000 -> drive_can_gpio7
Bank: 1 Reg: 0x0c30300c Val: 0x00000000 -> drive_can1_dout
Bank: 1 Reg: 0x0c303014 Val: 0x00000000 -> drive_can1_din
Bank: 1 Reg: 0x0c30301c Val: 0x00000000 -> drive_can0_dout
Bank: 1 Reg: 0x0c303024 Val: 0x00000000 -> drive_can0_din
Bank: 1 Reg: 0x0c30302c Val: 0xf0000000 -> drive_can_gpio0
Bank: 1 Reg: 0x0c303034 Val: 0xf0000000 -> drive_can_gpio1
Bank: 1 Reg: 0x0c30303c Val: 0x00000000 -> drive_can_gpio2
Bank: 1 Reg: 0x0c303044 Val: 0x00000000 -> drive_can_gpio3
Bank: 1 Reg: 0x0c30304c Val: 0x00000000 -> drive_can_gpio4
Bank: 1 Reg: 0x0c303054 Val: 0x00000000 -> drive_can_gpio5
Bank: 1 Reg: 0x0c30305c Val: 0x00000000 -> drive_can_gpio6
Bank: 0 Reg: 0x02431004 Val: 0x01f1f000 -> drive_gpio_aud3
Bank: 0 Reg: 0x0243100c Val: 0x01f1f000 -> drive_gpio_aud2
Bank: 0 Reg: 0x02431014 Val: 0x00000000 -> drive_gpio_aud1
Bank: 0 Reg: 0x0243101c Val: 0x00000000 -> drive_gpio_aud0
Bank: 0 Reg: 0x02431024 Val: 0x00708000 -> drive_aud_mclk
Bank: 0 Reg: 0x0243102c Val: 0x01616000 -> drive_dap1_fs
Bank: 0 Reg: 0x02431034 Val: 0x01616000 -> drive_dap1_din
Bank: 0 Reg: 0x0243103c Val: 0x01616000 -> drive_dap1_dout
Bank: 0 Reg: 0x02431044 Val: 0x01616000 -> drive_dap1_sclk
Bank: 0 Reg: 0x02432004 Val: 0xf0000000 -> drive_dmic1_clk
Bank: 0 Reg: 0x0243200c Val: 0xf0000000 -> drive_dmic1_dat
Bank: 0 Reg: 0x02432014 Val: 0xf0000000 -> drive_dmic2_dat
Bank: 0 Reg: 0x0243201c Val: 0xf0000000 -> drive_dmic2_clk
Bank: 0 Reg: 0x02432024 Val: 0xf0000000 -> drive_dmic4_dat
Bank: 0 Reg: 0x0243202c Val: 0xf0000000 -> drive_dmic4_clk
Bank: 0 Reg: 0x02432034 Val: 0xf0000000 -> drive_dap4_fs
Bank: 0 Reg: 0x0243203c Val: 0xf0000000 -> drive_dap4_din
Bank: 0 Reg: 0x02432044 Val: 0xf0000000 -> drive_dap4_dout
Bank: 0 Reg: 0x0243204c Val: 0xf0000000 -> drive_dap4_sclk
Bank: 0 Reg: 0x02430004 Val: 0x00000000 -> drive_extperiph2_clk
Bank: 0 Reg: 0x0243000c Val: 0x00000000 -> drive_extperiph1_clk
Bank: 0 Reg: 0x02430014 Val: 0x0001f000 -> drive_cam_i2c_sda
Bank: 0 Reg: 0x0243001c Val: 0x0001f000 -> drive_cam_i2c_scl
Bank: 0 Reg: 0x02430024 Val: 0x00000000 -> drive_gpio_cam1
Bank: 0 Reg: 0x0243002c Val: 0x00000000 -> drive_gpio_cam2
Bank: 0 Reg: 0x02430034 Val: 0x00000000 -> drive_gpio_cam3
Bank: 0 Reg: 0x0243003c Val: 0x00000000 -> drive_gpio_cam4
Bank: 0 Reg: 0x02430044 Val: 0x00000000 -> drive_gpio_cam5
Bank: 0 Reg: 0x0243004c Val: 0x00000000 -> drive_gpio_cam6
Bank: 0 Reg: 0x02430054 Val: 0x00000000 -> drive_gpio_cam7
Bank: 0 Reg: 0x02434004 Val: 0x01616000 -> drive_dap2_din
Bank: 0 Reg: 0x0243400c Val: 0x01616000 -> drive_dap2_dout
Bank: 0 Reg: 0x02434014 Val: 0x01616000 -> drive_dap2_fs
Bank: 0 Reg: 0x0243401c Val: 0x01616000 -> drive_dap2_sclk
Bank: 0 Reg: 0x02434024 Val: 0x00606000 -> drive_uart4_cts
Bank: 0 Reg: 0x0243402c Val: 0x00606000 -> drive_uart4_rts
Bank: 0 Reg: 0x02434034 Val: 0x00606000 -> drive_uart4_rx
Bank: 0 Reg: 0x0243403c Val: 0x00606000 -> drive_uart4_tx
Bank: 0 Reg: 0x02434044 Val: 0x00000000 -> drive_gpio_wan4
Bank: 0 Reg: 0x0243404c Val: 0x00000000 -> drive_gpio_wan3
Bank: 0 Reg: 0x02434054 Val: 0x00000000 -> drive_gpio_wan2
Bank: 0 Reg: 0x0243405c Val: 0x00000000 -> drive_gpio_wan1
Bank: 0 Reg: 0x02434064 Val: 0x0001f000 -> drive_gen1_i2c_scl
Bank: 0 Reg: 0x0243406c Val: 0x0001f000 -> drive_gen1_i2c_sda
Bank: 0 Reg: 0x02435004 Val: 0x00606000 -> drive_uart1_cts
Bank: 0 Reg: 0x0243500c Val: 0x00606000 -> drive_uart1_rts
Bank: 0 Reg: 0x02435014 Val: 0x00606000 -> drive_uart1_rx
Bank: 0 Reg: 0x0243501c Val: 0x00606000 -> drive_uart1_tx
Bank: 0 Reg: 0x0243502c Val: 0x00000000 -> drive_directdc1_out3
Bank: 0 Reg: 0x02435034 Val: 0x00000000 -> drive_directdc1_out2
Bank: 0 Reg: 0x0243503c Val: 0x00000000 -> drive_directdc1_out1
Bank: 0 Reg: 0x02435044 Val: 0x00000000 -> drive_directdc1_out0
Bank: 0 Reg: 0x0243504c Val: 0x00000000 -> drive_directdc1_in
Bank: 0 Reg: 0x02435054 Val: 0x00000000 -> drive_directdc1_clk
Bank: 0 Reg: 0x02433004 Val: 0xf0000000 -> drive_gpio_pq0
Bank: 0 Reg: 0x0243300c Val: 0xf0000000 -> drive_gpio_pq1
Bank: 0 Reg: 0x02433014 Val: 0xf0000000 -> drive_gpio_pq2
Bank: 0 Reg: 0x0243301c Val: 0xf0000000 -> drive_gpio_pq3
Bank: 0 Reg: 0x02433024 Val: 0x00000000 -> drive_gpio_pq4
Bank: 0 Reg: 0x0243302c Val: 0x00000000 -> drive_gpio_pq5
Bank: 0 Reg: 0x02433034 Val: 0x00000000 -> drive_gpio_pq6
Bank: 0 Reg: 0x0243303c Val: 0x00000000 -> drive_gpio_pq7
Bank: 0 Reg: 0x02440004 Val: 0x00606000 -> drive_gpio_edp2
Bank: 0 Reg: 0x0244000c Val: 0x00606000 -> drive_gpio_edp3
Bank: 0 Reg: 0x02440014 Val: 0x00606000 -> drive_gpio_edp0
Bank: 0 Reg: 0x0244001c Val: 0x00606000 -> drive_gpio_edp1
Bank: 0 Reg: 0x02440024 Val: 0x00000000 -> drive_dp_aux_ch0_hpd
Bank: 0 Reg: 0x0244002c Val: 0x00000000 -> drive_dp_aux_ch1_hpd
Bank: 0 Reg: 0x02440034 Val: 0x00000000 -> drive_hdmi_cec
Bank: 0 Reg: 0x02437004 Val: 0x00000000 -> drive_pex_l2_clkreq_n
Bank: 0 Reg: 0x0243700c Val: 0x00000000 -> drive_pex_wake_n
Bank: 0 Reg: 0x02437014 Val: 0x00000000 -> drive_pex_l1_clkreq_n
Bank: 0 Reg: 0x0243701c Val: 0x00000000 -> drive_pex_l1_rst_n
Bank: 0 Reg: 0x02437024 Val: 0x00000000 -> drive_pex_l0_clkreq_n
Bank: 0 Reg: 0x0243702c Val: 0x00000000 -> drive_pex_l0_rst_n
Bank: 0 Reg: 0x02437034 Val: 0x00000000 -> drive_pex_l2_rst_n
Bank: 0 Reg: 0x02438004 Val: 0x00000000 -> drive_sdmmc1_clk
Bank: 0 Reg: 0x0243800c Val: 0x00000000 -> drive_sdmmc1_cmd
Bank: 0 Reg: 0x02438018 Val: 0x00000000 -> drive_sdmmc1_dat3
Bank: 0 Reg: 0x02438020 Val: 0x00000000 -> drive_sdmmc1_dat2
Bank: 0 Reg: 0x02438028 Val: 0x00000000 -> drive_sdmmc1_dat1
Bank: 0 Reg: 0x02438030 Val: 0x00000000 -> drive_sdmmc1_dat0
Bank: 0 Reg: 0x02439004 Val: 0x00000000 -> drive_eqos_td3
Bank: 0 Reg: 0x0243900c Val: 0x00000000 -> drive_eqos_td2
Bank: 0 Reg: 0x02439014 Val: 0x00000000 -> drive_eqos_td1
Bank: 0 Reg: 0x0243901c Val: 0x00000000 -> drive_eqos_td0
Bank: 0 Reg: 0x02439024 Val: 0x00000000 -> drive_eqos_rd3
Bank: 0 Reg: 0x0243902c Val: 0x00000000 -> drive_eqos_rd2
Bank: 0 Reg: 0x02439034 Val: 0x00000000 -> drive_eqos_rd1
Bank: 0 Reg: 0x0243903c Val: 0x00000000 -> drive_eqos_mdio
Bank: 0 Reg: 0x02439044 Val: 0x00000000 -> drive_eqos_rd0
Bank: 0 Reg: 0x0243904c Val: 0x00000000 -> drive_eqos_mdc
Bank: 0 Reg: 0x02439058 Val: 0x00000000 -> drive_eqos_txc
Bank: 0 Reg: 0x02439060 Val: 0x00000000 -> drive_eqos_rxc
Bank: 0 Reg: 0x02439068 Val: 0x00000000 -> drive_eqos_tx_ctl
Bank: 0 Reg: 0x02439070 Val: 0x00000000 -> drive_eqos_rx_ctl
Bank: 0 Reg: 0x0243a004 Val: 0x00000000 -> drive_sdmmc3_dat3
Bank: 0 Reg: 0x0243a00c Val: 0x00000000 -> drive_sdmmc3_dat2
Bank: 0 Reg: 0x0243a014 Val: 0x00000000 -> drive_sdmmc3_dat1
Bank: 0 Reg: 0x0243a01c Val: 0x00000000 -> drive_sdmmc3_dat0
Bank: 0 Reg: 0x0243a028 Val: 0x00000000 -> drive_sdmmc3_cmd
Bank: 0 Reg: 0x0243a030 Val: 0x00000000 -> drive_sdmmc3_clk
Bank: 0 Reg: 0x0243b004 Val: 0x00000000 -> drive_qspi_io3
Bank: 0 Reg: 0x0243b00c Val: 0x00000000 -> drive_qspi_io2
Bank: 0 Reg: 0x0243b014 Val: 0x00000000 -> drive_qspi_io1
Bank: 0 Reg: 0x0243b01c Val: 0x00000000 -> drive_qspi_io0
Bank: 0 Reg: 0x0243b024 Val: 0x00000000 -> drive_qspi_sck
Bank: 0 Reg: 0x0243b02c Val: 0x00000000 -> drive_qspi_cs_n
Bank: 1 Reg: 0x0c301004 Val: 0x00000000 -> drive_gpio_sw1
Bank: 1 Reg: 0x0c30100c Val: 0x00000000 -> drive_gpio_sw2
Bank: 1 Reg: 0x0c301014 Val: 0x00000000 -> drive_gpio_sw3
Bank: 1 Reg: 0x0c30101c Val: 0x00000000 -> drive_gpio_sw4
Bank: 1 Reg: 0x0c301024 Val: 0x00000000 -> drive_shutdown
Bank: 1 Reg: 0x0c30102c Val: 0x00000000 -> drive_pmu_int
Bank: 1 Reg: 0x0c301034 Val: 0x00000000 -> drive_safe_state
Bank: 1 Reg: 0x0c30103c Val: 0x00000000 -> drive_vcomp_alert
Bank: 1 Reg: 0x0c301044 Val: 0x00000000 -> drive_soc_pwr_req
Bank: 1 Reg: 0x0c30104c Val: 0x00000000 -> drive_batt_oc
Bank: 1 Reg: 0x0c301054 Val: 0x00000000 -> drive_clk_32k_in
Bank: 1 Reg: 0x0c30105c Val: 0x00000000 -> drive_power_on
Bank: 1 Reg: 0x0c301064 Val: 0x0001f000 -> drive_pwr_i2c_scl
Bank: 1 Reg: 0x0c30106c Val: 0x0001f000 -> drive_pwr_i2c_sda
Bank: 1 Reg: 0x0c301084 Val: 0x00000000 -> drive_gpio_dis0
Bank: 1 Reg: 0x0c30108c Val: 0x00000000 -> drive_gpio_dis1
Bank: 1 Reg: 0x0c301094 Val: 0x00000000 -> drive_gpio_dis2
Bank: 1 Reg: 0x0c30109c Val: 0x00000000 -> drive_gpio_dis3
Bank: 1 Reg: 0x0c3010a4 Val: 0x00000000 -> drive_gpio_dis4
Bank: 1 Reg: 0x0c3010ac Val: 0x00000000 -> drive_gpio_dis5
Bank: 0 Reg: 0x0243d004 Val: 0x00000000 -> drive_gpio_wan8
Bank: 0 Reg: 0x0243d00c Val: 0x00000000 -> drive_gpio_wan7
Bank: 0 Reg: 0x0243d014 Val: 0x00000000 -> drive_gpio_wan6
Bank: 0 Reg: 0x0243d01c Val: 0x00000000 -> drive_gpio_wan5
Bank: 0 Reg: 0x0243d024 Val: 0x00606000 -> drive_uart2_tx
Bank: 0 Reg: 0x0243d02c Val: 0x00606000 -> drive_uart2_rx
Bank: 0 Reg: 0x0243d034 Val: 0x00606000 -> drive_uart2_rts
Bank: 0 Reg: 0x0243d03c Val: 0x00606000 -> drive_uart2_cts
Bank: 0 Reg: 0x0243d044 Val: 0x00000000 -> drive_uart5_rx
Bank: 0 Reg: 0x0243d04c Val: 0x00000000 -> drive_uart5_tx
Bank: 0 Reg: 0x0243d054 Val: 0x00000000 -> drive_uart5_rts
Bank: 0 Reg: 0x0243d05c Val: 0x00000000 -> drive_uart5_cts
Bank: 0 Reg: 0x0243d064 Val: 0x00000000 -> drive_gpio_mdm1
Bank: 0 Reg: 0x0243d06c Val: 0x00000000 -> drive_gpio_mdm2
Bank: 0 Reg: 0x0243d074 Val: 0x00000000 -> drive_gpio_mdm3
Bank: 0 Reg: 0x0243d07c Val: 0x00000000 -> drive_gpio_mdm4
Bank: 0 Reg: 0x0243d084 Val: 0x00000000 -> drive_gpio_mdm5
Bank: 0 Reg: 0x0243d08c Val: 0x00000000 -> drive_gpio_mdm6
Bank: 0 Reg: 0x0243d094 Val: 0x00000000 -> drive_gpio_mdm7
Bank: 0 Reg: 0x0243d09c Val: 0x00000000 -> drive_bcpu_pwr_req
Bank: 0 Reg: 0x0243d0a4 Val: 0x00000000 -> drive_mcpu_pwr_req
Bank: 0 Reg: 0x0243d0ac Val: 0x00000000 -> drive_gpu_pwr_req
Bank: 0 Reg: 0x0243d0b4 Val: 0x0001f000 -> drive_gen7_i2c_scl
Bank: 0 Reg: 0x0243d0bc Val: 0x0001f000 -> drive_gen7_i2c_sda
Bank: 0 Reg: 0x0243d0c4 Val: 0x0001f000 -> drive_gen9_i2c_sda
Bank: 0 Reg: 0x0243d0cc Val: 0x0001f000 -> drive_gen9_i2c_scl
Bank: 0 Reg: 0x0243d0d4 Val: 0x00000000 -> drive_usb_vbus_en0
Bank: 0 Reg: 0x0243d0dc Val: 0x00000000 -> drive_usb_vbus_en1
Bank: 0 Reg: 0x0243d0e4 Val: 0x00000000 -> drive_gp_pwm7
Bank: 0 Reg: 0x0243d0ec Val: 0x00000000 -> drive_gp_pwm6
Bank: 0 Reg: 0x02441004 Val: 0x0a00a000 -> drive_ufs0_rst
Bank: 0 Reg: 0x0244100c Val: 0x0a00a000 -> drive_ufs0_ref_clk

Hi walterkim,

Looks like your pinmux setting needs modification.
In MB1 CFG file tegra186-mb1-bct-pinmux-quill-p3310-1000-c03.cfg
pinmux.0x0c3010a8 = 0x00000411; # gpio_dis5_pu5: gp, tristate-enable, input-disable

Please make this as
pinmux.0x0c3010a8 = 0x00000401; # gpio_dis5_pu5: gp, tristate-disable, input-disable

Thanks.

Thank you WayneWWW

LCD1_BKLT_PWM is good.

pinmux…

Hai Walterkim,

   I want to use PWM on my carrier board, so please suggest which pin is compatiable for PWM.

Thanks in advance.

Regards,
Surendra Allam.

Hai Walterkim,

   I want to use PWM on my carrier board, so please suggest which pin is compatiable for PWM.

Thanks in advance.

Regards,
Surendra Allam.

Hi

We would like to use GP_PWM1 on Pin GPIO3_PU.00 (B27) for a SPEAKER. When we measure the Output of the PWM, we see that the frequency is always 72 kHz. Writing other values to /sys/class/pwmchip0/pwm0/period do not change the frequency. When writing into the duty_cycle, we see that the output signal changes accordingly. Are we missing something?