I working on a design using the Jetson Nano SoM that needs multiple USB 3.0 device interfaces (and possibly one USB 3.0 host interface).
In the documentation for the XUSB peripheral, it looks like it supports 4 USB 3.0 interfaces (SS1-SS4) (Figure 53 in the Technical Reference manual, Tegra_X1_TRM_DP07225001_v1.3p.pdf) but it looks like only 1 port (the OTG port) can be set as a device while all others are host.
In the Jetson Nano dev kit schematic (Jetson_Nano_Carrier_Board_Concept_Schematics.pdf, pg6), it looks like the PCIe shared pins are setup only for 4 lane PCIe and a single USB 3.0 port.
Is it possible to reconfigure the outputs of the SoM per the Nano technical reference manual(pg 1326) for Use Case 1A that supports PCIe 2lanes and USB SS2, SS3, SS1, and SS0 (where one port can be device/OTG and the others be hosts) or is it possible to somehow configure the XUSB for more than 1 device port?
We would suggest you follow the guidance to design the board. The default board is the hardware we have fully verified. Would be better to copy most of the design.
Thanks for the quick reply. I’ve reviewed the TM (technical reference manual, Tegra_X1_TRM_DP07225001_v1.3p.pdf) again and the Product Design guide and I am still not sure whether or how the Nano SoM can be configured to support both 1 device and 3 host USB 3.0 ports by muxing the PCIe/USB3 pins. In the Nano dev kit, it looks like only 1 USB3 host port is exposed which is connected to a USB3 hub which presents multiple USB A connection.
In our design, we would like to use the Use Case 1A configuration from section 22.7 in the TM where:
PCIE Lane 1 set to PCIE x2 (controller 0) - TegraX1 pins PEX_RX/TX1_N/P, module pins PCIE0_RX/TX3_N/P
PCIE Lane 2 set to PCIE x2 (controller 0) - TegraX1 pins PEX_RX/TX2_N/P, module pins PCIE0_RX/TX2_N/P
PCIE Lane 3 set to USB SS (Port 2) Host - TegraX1 pins PEX_RX/TX2_N/P, module pins PCIE0_RX/TX0_N/P
PCIE Lane 4 set to USB SS (Port 3) Host - TegraX1 pins PEX_RX/TX2_N/P, module pins PCIE0_RX/TX1_N/P
PCIE Lane 5 set to USB SS (Port 1) Host - TegraX1 pins PEX_RX/TX5_N/P, no module pins seem to expose this lane
PCIE Lane 6 set to USB SS (Port 0) Device - TegraX1 pins PEX_RX/TX6_N/P, module pins USBSS_RX/TX_N/P
Is there a way to configure the Nano SoM as above?
A colleague of mine did note that in the Jetson TX2 dev kit, multiple USB ports are configured (USB_SS1_RX/TX is assigned to PEX_RX/TX2 and USB_SS0_RX/TX assigned to PEX_RX/TX0).
Hi,
For using Jetson Nano, we would suggest you follow the USB lane mapping of default carrier board. This is the design we have verified. For customizing USB lane mapping, you may consider TX1 or TX2.
This answer doesn’t help me understand whether I will be able to use the Nano SOM in my design, even if not supported by the Nano Dev Kit. Can you provide me with a contact that can help answer the question I’ve presented above please?