Hi Nvidia,
We are doing the PCIe Compliance Testing and we also referred the NX tuning guide DA-09890-001_v1.2.
The issue is we can’t change test pattern in GEN3 speed, it stays in pattern0.
We also have test the NX EVK and we got the same result, could anyone teach us how to change the pattern in GEN3?
BTW, we have tried to use the both clocks (NX’s clock and external clock generator) to RX for changing pattern, but it doesn’t work.
100MHz Clock on RX for ~1ms should have helped in changing Gen3 test pattern
We have a couple of follow-up questions on this
- Would like to know if RX of NV PCIe is not connected to anything else, but only to clock generator?
- Can we confirm if the PCIe controller state is in polling.compliance? if so how did you achieve the Gen3 P0 patterns? Are you following a different method other than the one mentioned above? Because if you are using the same method then you should not get stuck at P0
Hi Vidyas,
- Our HW configuration is NX + Carried board + M.2M key card + PCIe x4 CLB and using external clock generator.
- It’s an amazing thing, we can change patterns form GEN1, GEN2 -3.5dB, GEN2 -6dB, to GEN3 P0, and the pattern finally stays in GEN3 P0, we have tried to change clock Vp-p, degree, continue clock, burst mode clock, they all never change GEN3 pattern to P7 or P8.
- Can you tech me how to check PCIe controller state is in polling.compliance? Does any register can be confirmed?
Here is the update from our team…
Which signal is being used to move from Gen1 to Gen2 -3.5dB and so on?
Easier way to use the CMTS signal from the Gen4 PCI-SIG CBB J5 and J85 SMP pins. This should maintain the signal with spec to move forward
Hi Vidyas,
- We used 100MHz Clock on RX LAN0 for ~1ms, but it stop on GEN3 P0.
- How to use the CMTS signal? Could you share any documents for us?
If Compliance pattern in already Gen3 P0, giving 100MHz clock again on RX of DUT should change patterns further to Gen3 P1, and so on…
This works fine in our lab testing, and no issues are reported so far.