Continuing the discussion from Set Speed and Role of enP7p1s0:
DRIVE OS Version: Provide DRIVE OS version: 6.0.10
Issue Description:
I would like to clarify the intended use of the switch-internal PTP time on DRIVE AGX Orin.
According to the DRIVE OS documentation, the onboard Marvell switches have their own MCU/firmware for AVNU CDS 1.6 PTP and the switch ports use static PTP roles.
In our setup, we can see gPTP frames coming from switch-internal clock identities, for example on mgbe2_0 and mgbe3_0 . These identities do not match the Linux interface MACs, so they seem to come from the switch PTP instances rather than from the Tegra MACs.
Instead of feeding Tegra time into a switch port, as discussed in this related thread:
would it be possible to use the switch-internal PTP time as the source and synchronize the Tegra MGBE PHCs to it?
In other words: can mgbe2_0 / mgbe3_0 act as PTP clients/secondaries to the switch-internal PTP masters, so that the Linux-visible PHCs follow the switch timebase?
If this is supported, would that correspond to the recommended/default PTP topology shown in the documentation, or is an additional service/configuration such as ptp4l /phc2sys required?