Can the GPIO toggle speed of the SPE system reach 408Mhz in orin nano?

if TRUE, how to config it to 408Mhz?

I don’t know about specific limits, but you might find this of interest:
https://forums.developer.nvidia.com/t/how-to-modify-gpios-toggle-speed/258941/5

Not works for me. strange.

I use SPE R5 to output gpio toggle, the max toggle speed I got is 270khz, It do not meet I need, does it any chance to set higher?

Hello,
To set clocks, please use root (sudo) to have a try.
Anyway, that may not help, though I’ve not tried this.

GPIO toggle frequency by SPE may be limited by several aspects, like register access delay, CPU processing capability, etc.
200+KHz looks not a very low result per my guess. And the key is, that a little far away from your expectation, say, 1MHz.

Let’s go back to PWM issue, and keep tracking in previous thread.

br
Chenjian

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Good, Looking forward to your reply.

One would always need sudo to write to a /sys file. In the case where permission is denied while using sudo, it implies the driver itself does not have a function to accept that input. The files in “/sys” are pseudo files and not real files, and are actually code in the individual driver.

Apparently either (A) this driver is designed differently, and this rate is set at some different driver, or (B) there is no ability to set that rate. NVIDIA would have to comment what works on this model, I do not have an Orin Nano to test or examine. I see though that @jachen has already answered. Perhaps it is a limitation of trying that particular speed, although I suspect that the error message would be different if it were just an out of range value. You might “cat” the existing value, and try to echo that back in to see if it accepts the existing value (meaning you know the value would work if accepted, so you are testing write ability).

Hello, HeapCorrupt:
My suggestion is to implement PWM driver in Linux side directly, instead of using GPIO to simulate it, since max frequency is limited with software simulation.
Sorry that I cannot provide sample driver to you, due to my limited bandwidth.
Here are just the steps of very low-level register accessing. You can refer to the following steps and make your own driver.

  1. Let’s use PWM7 as an example. The corresponding pin is pin 32 in 40-pin header. (Orin NX/Nano devkit)
  2. Update file bootloader/tegra234-firewall-config-base.dtsi, to enable CCPLEX access:
    reg@5126 { /* CBB_FABRIC, CBB_CENTRAL_CBB_FIREWALL_PWM7_BLF, READ_CTL /
    exclusion-info = <2>;
    value = <0x0010000a>;
    };
    reg@5127 { /
    CBB_FABRIC, CBB_CENTRAL_CBB_FIREWALL_PWM7_BLF, WRITE_CTL */
    exclusion-info = <2>;
    value = <0x0010000a>;
    };
  3. After kernel’s up, update pinmux:
    busybox devmem 0x02434080 32 0x400
  4. Update PWM7 related settings:
    echo 1 >/sys/kernel/debug/bpmp/debug/clk/pwm7/state
    busybox devmem 0x032e0000 32 0x804d0000

Then you should be able to observe the waveform from that pin.

You can also update some configs, like freq, duty-ratio, with different input.

Again, after hardware verification’s done, you should make a decent driver then.

br
ChenJian

Hi @jachen

Thank you for your reply, and for providing some detailed register settings.

Need to clarify again my exact needs:

How to use the pwm peripheral to output a single pwm waveform, for example a single square wave with an 14% duty cycle.

My requirement is to output a single square wave with a variable duty cycle to simulate output logic 0 and logic 1.

Logic 0:

Logic 1:

ReSet:

When I implemented this function, the problem I encountered was: pwm will output continuously and the number of cycles is uncontrollable.

Could we control the registers to output a single pwm pulse?

The best way is to use a small CPLD or FPGA to generate the waveforms. This way the whole timing is done purely in hardware and absolutely deterministic.

Next best way is to use a small PIC etc with Configurable Logic Cells. The benefit of using a small 8/16 bit micro is the tight integration between CPU core and IO. In larger MCUs the CPU core is not done in-house, but purchased fron ARM or MIPS and used as a black box. CPU and peripherial are connected via asynchronous (!) busses that run much slower than the internal CPU clock. Plus you can’t do atomic read-write cycles like setting or clearing single bits. ARM needs bit-banding to circumvent this problem. With 8 and 16 bit PICs the IO registers are just part of the memory or the CPU register space, so it’s no problem there.

fchk

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Hello, HeapCorrupt:
Sorry that I mis-understand your request.
To generate a single square wave with so high frequency and desired duty cycle, it’s hard to implement with current BSP, per my understanding.

I guess fchkjwlsq 's comment may be reasonable.

br
Chenjian

Once I hoped to use the SPE( Sensor Processing Engine) system, but the SPE does not include the pwm peripheral. SPE is the most suitable for such a scene, What a pity!

Hello,
SPE can control PWM, but that’s same as CCPLEX, and you cannot control the exact count of output waveform.

But I think you can use UART TXD to generate such waveform. You may consider it.
Configure proper baudrate, and output data like (bin) 1100000000, either 64bit, or 128bit, and duty cycle can be configurable. But such implementation looks weird.

br
Chenjian

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Hi @jachen

Whoa, guess what I’m going to do now? I plan to use SPI’s MOSI to output this serial data, at the cost of wasting a few SPI’s GPIO. Now it seems that the TX output of UART is better, because the price is only wasted one RX pin. Thansk!

Beware that at higher clock speeds the integrated UART clock might not be as exact as needed. When using the UART at higher rates I often suggest using two stop bits (which makes clock timing less critical).

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Yes, I guess SPI or UART TXD may deserve a try.
You can take a look at Orin TRM, and max UART baud rate will be 12.75Mbps, and SPI can run at 50MHz clock.
That may be related to the accuracy of duty cycle control.
Anyway, it’s off the topic of this thread, and please end this thread.

br
ChenJian

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