Cannot be detected by some SD cards

hello.

Depending on the SD card, it cannot be detected and the following error will occur.
dmesg_NG_SD_CLK_45M.txt (52.3 KB)

CLK 100k log.

[  471.632374] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.639533] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.646427] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.654863] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.661961] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.720869] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.727821] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.734840] mmc1: CMD CRC or end bit error, int mask 0xc0000
[  471.743747] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.750986] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.812717] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.820181] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.827395] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.836720] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.844267] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.905492] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.913342] mmc1: CMD CRC or end bit error, int mask 0xc0001
[  471.921097] mmc1: CMD CRC or end bit error, int mask 0xc0000
[  471.930525] mmc1: CMD CRC or end bit error, int mask 0xc0000
[  471.940012] mmc1: CMD CRC or end bit error, int mask 0xc0001

If you measure the CLK frequency when the SD card is inserted with an SD card that cannot be detected, it will be 45MHz and 100kHz.
The CLK frequency of the SD card that can be detected is 400kHz.
I tried 4 types of SD cards, but 2 types could not be detected.
The SD card uses UHS-IS.
Why does this make a difference?

The device tree for sdhci @ 700b0400.

	sdhci@700b0400 {
		compatible = "nvidia,tegra210-sdhci";
		reg = <0x0 0x700b0400 0x0 0x200>;
		interrupts = <0x0 0x13 0x4>;
		aux-device-name = "sdhci-tegra.2";
		iommus = <0x30 0x1b>;
		nvidia,runtime-pm-type = <0x0>;
		clocks = <0x26 0x45 0x26 0xf3 0x26 0x136 0x26 0xc1>;
		clock-names = "sdmmc", "pll_p", "pll_c4_out2", "sdmmc_legacy_tm";
		resets = <0x26 0x45>;
		reset-names = "sdhci";
		status = "okay";
		tap-delay = <0x3>;
		trim-delay = <0x3>;
		mmc-ocr-mask = <0x3>;
		max-clk-limit = <0xb532b80>;
		ddr-clk-limit = <0x2dc6c00>;
		bus-width = <0x4>;
		calib-3v3-offsets = <0x7d>;
		calib-1v8-offsets = <0x7b7b>;
		compad-vref-3v3 = <0x7>;
		compad-vref-1v8 = <0x7>;
		pll_source = "pll_p", "pll_c4_out2";
		ignore-pm-notify;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		nvidia,en-io-trim-volt;
		nvidia,en-periodic-calib;
		cd-inverted;
		wp-inverted;
		pwrdet-support;
		pinctrl-names = "sdmmc_schmitt_enable", "sdmmc_schmitt_disable", "sdmmc_clk_schmitt_enable", "sdmmc_clk_schmitt_disable", "sdmmc_drv_code", "sdmmc_default_drv_code", "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
		pinctrl-0 = <0x8d>;
		pinctrl-1 = <0x8e>;
		pinctrl-2 = <0x8f>;
		pinctrl-3 = <0x90>;
		pinctrl-4 = <0x91>;
		pinctrl-5 = <0x92>;
		pinctrl-6 = <0x93>;
		pinctrl-7 = <0x94>;
		vqmmc-supply = <0x5d>;
		vmmc-supply = <0x95>;
		mmc-ddr-1_8v;
		uhs-mask = <0x0>;
		cd-gpios = <0x5b 0x1b 0x0>;
		nvidia,vmmc-always-on;
		sd-uhs-sdr104;
		sd-uhs-sdr50;
		sd-uhs-sdr25;
		sd-uhs-sdr12;
		mmc-hs200-1_8v;
		no-sdio;
		no-mmc;
		linux,phandle = <0xbd>;
		phandle = <0xbd>;

		prod-settings {
			#prod-cells = <0x3>;

			prod_c_ds {
				prod = <0x100 0xff0000 0x10000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x3000007d>;
			};

			prod_c_hs {
				prod = <0x100 0xff0000 0x10000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x3000007d>;
			};

			prod_c_sdr12 {
				prod = <0x100 0xff0000 0x10000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30007b7b>;
			};

			prod_c_sdr25 {
				prod = <0x100 0xff0000 0x10000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30007b7b>;
			};

			prod_c_sdr50 {
				prod = <0x100 0xff0000 0x10000 0x1c0 0xe000 0x8000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30007b7b>;
			};

			prod_c_sdr104 {
				prod = <0x100 0xff0000 0x10000 0x1c0 0xe000 0x4000 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30007b7b>;
			};

			prod_c_ddr52 {
				prod = <0x100 0x1fff0000 0x0 0x1e0 0xf 0x7 0x1e4 0x30077f7f 0x30007b7b>;
			};

			prod {
				prod = <0x100 0x1fff000e 0x3090028 0x1c0 0x8001fc0 0x8000040 0x1c4 0x77 0x0 0x120 0x20001 0x1 0x128 0x43000000 0x0 0x1f0 0x80000 0x80000>;
			};
		};
	};

You can use your old topic to track. That was still wrong at that time.

There is no need to change max-clk-limit to make it work.

hello Wayne.

I did it without changing max-clk-limit, but all four types can no longer be detected.
It is a log at that time.

[  543.381480] mmc1: host does not support reading read-only switch, assuming write-enable
[  543.538132] mmc1: CMD CRC or end bit error, int mask 0xa0001
[  543.543784] mmc1: Data CRC error
[  543.547003] sdhci: =========== REGISTER DUMP (mmc1)===========
[  543.552821] sdhci: Sys addr: 0x00000008 | Version:  0x00000303
[  543.558640] sdhci: Blk size: 0x00007200 | Blk cnt:  0x00000008
[  543.564458] sdhci: Argument: 0x00000000 | Trn mode: 0x0000003b
[  543.570277] sdhci: Present:  0x01fb0008 | Host ctl: 0x00000017
[  543.576094] sdhci: Power:    0x00000001 | Blk gap:  0x00000000
[  543.581911] sdhci: Wake-up:  0x00000000 | Clock:    0x00000007
[  543.587728] sdhci: Timeout:  0x0000000e | Int stat: 0x00001000
[  543.593547] sdhci: Int enab: 0x02ff100b | Sig enab: 0x02fc100b
[  543.599365] sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000
[  543.605183] sdhci: Caps:     0x376cd08c | Caps_1:   0x10006f77
[  543.611000] sdhci: Cmd:      0x0000123a | Max curr: 0x00000000
[  543.616817] sdhci: Host ctl2: 0x0000308b
[  543.620730] sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000ffefe410
[  543.627261] sdhci: ===========================================
[  543.633094] mmc1: CMD CRC or end bit error, int mask 0xa0001
[  553.847088] tegra-i2c 7000d000.i2c: pio timed out addr: 0x3c tlen:28 rlen:4
[  553.854123] tegra-i2c 7000d000.i2c: --- register dump for debugging ----
[  553.860837] tegra-i2c 7000d000.i2c: I2C_CNFG - 0x22c00
[  553.865987] tegra-i2c 7000d000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x1010001
[  553.872866] tegra-i2c 7000d000.i2c: I2C_FIFO_CONTROL - 0xe0
[  553.878558] tegra-i2c 7000d000.i2c: I2C_FIFO_STATUS - 0x800081
[  553.884397] tegra-i2c 7000d000.i2c: I2C_INT_MASK - 0x7d
[  553.889629] tegra-i2c 7000d000.i2c: I2C_INT_STATUS - 0xc3
[  553.895038] tegra-i2c 7000d000.i2c: i2c transfer timed out addr: 0x3c
[  553.901542] max77620-gpio max77620-gpio: CNFG_GPIOx read failed: -110
[  564.087375] tegra-i2c 7000d000.i2c: pio timed out addr: 0x3c tlen:28 rlen:4
[  564.094344] tegra-i2c 7000d000.i2c: --- register dump for debugging ----
[  564.101061] tegra-i2c 7000d000.i2c: I2C_CNFG - 0x22c00
[  564.106208] tegra-i2c 7000d000.i2c: I2C_PACKET_TRANSFER_STATUS - 0x1010001
[  564.113087] tegra-i2c 7000d000.i2c: I2C_FIFO_CONTROL - 0xe0
[  564.118663] tegra-i2c 7000d000.i2c: I2C_FIFO_STATUS - 0x800081
[  564.124501] tegra-i2c 7000d000.i2c: I2C_INT_MASK - 0x7d
[  564.129731] tegra-i2c 7000d000.i2c: I2C_INT_STATUS - 0xc3
[  564.135139] tegra-i2c 7000d000.i2c: i2c transfer timed out addr: 0x3c
[  564.141638] max77620-gpio max77620-gpio: CNFG_GPIO_OUT update failed: -110
[  585.204856] NMI watchdog: BUG: soft lockup - CPU#1 stuck for 24s! [Xorg:5532]
[  585.204907] INFO: rcu_preempt detected stalls on CPUs/tasks:
[  585.204909] INFO: rcu_sched detected stalls on CPUs/tasks:
[  585.204915]  0-...: (1 GPs behind) idle=dcd/2/0 softirq=20807/20808 fqs=2437
[  585.204919]  0-...: (1 GPs behind) idle=dcd/2/0 softirq=20732/20808 fqs=2444
[  585.204921]
[  585.204923]
[  585.204923] (detected by 3, t=10416 jiffies, g=6877, c=6876, q=630)
[  585.204926] (detected by 2, t=10415 jiffies, g=1100, c=1099, q=4)
[  585.204927] Task dump for CPU 0:
[  585.204928] Task dump for CPU 0:
[  585.204930] swapper/0       R
[  585.204931] swapper/0       R
[  585.204932]   running task
[  585.204934]   running task
[  585.204935]     0     0      0 0x00000002
[  585.204936]     0     0      0 0x00000002
[  585.204937] Call trace:
[  585.204938] Call trace:
[  585.204945] [<ffffff8008085ffc>] __switch_to+0x9c/0xc0
[  585.204950] [<ffffff8008085ffc>] __switch_to+0x9c/0xc0
[  585.204955] [<ffffff8008ba6c00>] cpuidle_enter_state+0xa0/0x380
[  585.204959] [<ffffff8008ba6c00>] cpuidle_enter_state+0xa0/0x380
[  585.204961] [<ffffff8008ba6f54>] cpuidle_enter+0x34/0x48
[  585.204964] [<ffffff8008ba6f54>] cpuidle_enter+0x34/0x48
[  585.204967] [<ffffff800811104c>] call_cpuidle+0x44/0x70
[  585.204969] [<ffffff800811104c>] call_cpuidle+0x44/0x70
[  585.204971] [<ffffff80081113c8>] cpu_startup_entry+0x1b0/0x200
[  585.204973] [<ffffff80081113c8>] cpu_startup_entry+0x1b0/0x200
[  585.204977] [<ffffff8008f5ccbc>] rest_init+0x84/0x90
[  585.204980] [<ffffff8008f5ccbc>] rest_init+0x84/0x90
[  585.204985] [<ffffff8009620b64>] start_kernel+0x370/0x384
[  585.204989] [<ffffff8009620b64>] start_kernel+0x370/0x384
[  585.204991] [<ffffff8009620204>] __primary_switched+0x80/0x94
[  585.204994] [<ffffff8009620204>] __primary_switched+0x80/0x94
[  585.204997] rcu_preempt kthread starved for 5263 jiffies! g6877 c6876 f0x0 RCU_GP_WAIT_FQS(3) ->state=0x1
[  585.205000] rcu_sched kthread starved for 5263 jiffies! g1100 c1099 f0x0 RCU_GP_WAIT_FQS(3) ->state=0x1
[  585.205002] rcu_preempt     S
[  585.205003] rcu_sched       S
[  585.205004]     0     7      2 0x00000000
[  585.205005]     0     8      2 0x00000000
[  585.205006] Call trace:
[  585.205006] Call trace:
[  585.205009] [<ffffff8008085ffc>] __switch_to+0x9c/0xc0
[  585.205011] [<ffffff8008085ffc>] __switch_to+0x9c/0xc0
[  585.205015] [<ffffff8008f60fa8>] __schedule+0x270/0x780
[  585.205017] [<ffffff8008f60fa8>] __schedule+0x270/0x780
[  585.205020] [<ffffff8008f614f8>] schedule+0x40/0xa8
[  585.205023] [<ffffff8008f614f8>] schedule+0x40/0xa8
[  585.205025] [<ffffff8008f64538>] schedule_timeout+0x88/0x420
[  585.205027] [<ffffff8008f64538>] schedule_timeout+0x88/0x420
[  585.205030] [<ffffff800813047c>] rcu_gp_kthread+0x4a4/0x7d8
[  585.205033] [<ffffff800813047c>] rcu_gp_kthread+0x4a4/0x7d8
[  585.205037] [<ffffff80080db074>] kthread+0xec/0xf0
[  585.205039] [<ffffff80080db074>] kthread+0xec/0xf0
[  585.205041] [<ffffff80080838a0>] ret_from_fork+0x10/0x30
[  585.205043] [<ffffff80080838a0>] ret_from_fork+0x10/0x30
[  585.205054] Kernel panic - not syncing: Watchdog detected hard LOCKUP on cpu 0
[  585.205058] CPU: 3 PID: 0 Comm: swapper/3 Not tainted 4.9.201-tegra #5
[  585.205060] Hardware name: NVIDIA Jetson Nano Developer Kit (DT)
[  585.205061] Call trace:
[  585.205064] [<ffffff800808b9f8>] dump_backtrace+0x0/0x198
[  585.205067] [<ffffff800808bfbc>] show_stack+0x24/0x30
[  585.205072] [<ffffff800845abe8>] dump_stack+0xa0/0xc8
[  585.205076] [<ffffff80081c0a00>] panic+0x12c/0x2a8
[  585.205080] [<ffffff800818169c>] watchdog_check_hardlockup_other_cpu+0x11c/0x120
[  585.205083] [<ffffff8008180810>] watchdog_timer_fn+0x98/0x2c0
[  585.205086] [<ffffff8008138b60>] __hrtimer_run_queues+0xd8/0x360
[  585.205089] [<ffffff80081394b0>] hrtimer_interrupt+0xa8/0x1e0
[  585.205093] [<ffffff8008c00a30>] tegra210_timer_isr+0x38/0x48
[  585.205096] [<ffffff8008121610>] __handle_irq_event_percpu+0x68/0x288
[  585.205099] [<ffffff8008121858>] handle_irq_event_percpu+0x28/0x60
[  585.205101] [<ffffff80081218e0>] handle_irq_event+0x50/0x80
[  585.205104] [<ffffff80081256f4>] handle_fasteoi_irq+0xd4/0x1c0
[  585.205106] [<ffffff80081205c4>] generic_handle_irq+0x34/0x50
[  585.205108] [<ffffff8008120cb0>] __handle_domain_irq+0x68/0xc0
[  585.205110] [<ffffff8008080d44>] gic_handle_irq+0x5c/0xb0
[  585.205112] [<ffffff8008082c28>] el1_irq+0xe8/0x194
[  585.205115] [<ffffff8008ba6c18>] cpuidle_enter_state+0xb8/0x380
[  585.205118] [<ffffff8008ba6f54>] cpuidle_enter+0x34/0x48
[  585.205120] [<ffffff800811104c>] call_cpuidle+0x44/0x70
[  585.205122] [<ffffff80081113c8>] cpu_startup_entry+0x1b0/0x200
[  585.205125] [<ffffff8008091cc8>] secondary_start_kernel+0x190/0x1f8
[  585.205127] [<0000000084f671a4>] 0x84f671a4

There was no change in CLK at the time of detection.
When it could be detected, max-clk-limit was set to 190MHz.
There was a distance from Jetson in charge of hardware to the SD slot, and there was a possibility that CLK would be attenuated, so I was able to detect it by setting max-clk-limit to 190MHz.
Does the max-clk-limit setting affect the command at the first detection?

Can you firstly fix your kernel panic problem here and share full dmesg and full dts?

Honestly, we shouldn’t see some i2c error and also pmix gpio error here.

hello Wayne.

It is difficult to investigate the cause of a kernel panic just by changing max-clk-limit.
If you look up 7000d000 @ i2c in the device tree, the regulator for the SD card is assigned here.
Is it possible to get a CRC error and access the regulator with i2c?
By the way, I haven’t changed 7000d000 @ i2c in the device tree.

device tree.

	i2c@7000d000 {
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		compatible = "nvidia,tegra210-i2c";
		reg = <0x0 0x7000d000 0x0 0x100>;
		interrupts = <0x0 0x35 0x4>;
		scl-gpio = <0x5b 0xc3 0x0>;
		sda-gpio = <0x5b 0xc4 0x0>;
		nvidia,require-cldvfs-clock;
		iommus = <0x30 0xe>;
		status = "okay";
		clock-frequency = <0xf4240>;
		dmas = <0x51 0x18 0x51 0x18>;
		dma-names = "rx", "tx";
		clocks = <0x26 0x2f 0x26 0xf3>;
		clock-names = "div-clk", "parent";
		resets = <0x26 0x2f>;
		reset-names = "i2c";
		nvidia,bit-bang-after-shutdown;
		linux,phandle = <0x124>;
		phandle = <0x124>;

		max77620@3c {
			compatible = "maxim,max77620";
			reg = <0x3c>;
			interrupts = <0x0 0x56 0x0>;
			nvidia,pmc-wakeup = <0x3c 0x1 0x33 0x8>;
			#interrupt-cells = <0x2>;
			interrupt-controller;
			gpio-controller;
			#gpio-cells = <0x2>;
			maxim,enable-clock32k-out;
			maxim,system-pmic-power-off;
			maxim,hot-die-threshold-temp = <0x1adb0>;
			#thermal-sensor-cells = <0x0>;
			pinctrl-names = "default";
			pinctrl-0 = <0x8b>;
			maxim,power-shutdown-gpio-states = <0x1 0x0>;
			linux,phandle = <0x23>;
			phandle = <0x23>;

			pinmux@0 {
				linux,phandle = <0x8b>;
				phandle = <0x8b>;

				pin_gpio0 {
					pins = "gpio0";
					function = "gpio";
				};

				pin_gpio1 {
					pins = "gpio1";
					function = "gpio";
					drive-open-drain = <0x1>;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
				};

				pin_gpio2 {
					pins = "gpio2";
					maxim,active-fps-source = <0x0>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
				};

				pin_gpio3 {
					pins = "gpio3";
					maxim,active-fps-source = <0x0>;
					maxim,active-fps-power-up-slot = <0x4>;
					maxim,active-fps-power-down-slot = <0x3>;
				};

				pin_gpio2_3 {
					pins = "gpio2", "gpio3";
					function = "fps-out";
					drive-open-drain = <0x1>;
					maxim,active-fps-source = <0x0>;
				};

				pin_gpio4 {
					pins = "gpio4";
					function = "32k-out1";
				};

				pin_gpio5_6_7 {
					pins = "gpio5", "gpio6", "gpio7";
					function = "gpio";
					drive-push-pull = <0x1>;
				};
			};

			spmic-default-output-high {
				gpio-hog;
				output-high;
				gpios = <0x1 0x0>;
				label = "spmic-default-output-high";
			};

			watchdog {
				maxim,wdt-timeout = <0x10>;
				maxim,wdt-clear-time = <0xd>;
				maxim,wdt-boot-init;
				status = "disabled";
				dt-override-status-odm-data = <0x20000 0x20000>;
				linux,phandle = <0xbb>;
				phandle = <0xbb>;
			};

			fps {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				fps0 {
					reg = <0x0>;
					maxim,shutdown-fps-time-periodi-us = <0x500>;
					maxim,fps-event-source = <0x0>;
				};

				fps1 {
					reg = <0x1>;
					maxim,shutdown-fps-time-period-us = <0x500>;
					maxim,fps-event-source = <0x1>;
					maxim,device-state-on-disabled-event = <0x0>;
				};

				fps2 {
					reg = <0x2>;
					maxim,fps-event-source = <0x0>;
				};
			};

			backup-battery {
				maxim,backup-battery-charging-current = <0x64>;
				maxim,backup-battery-charging-voltage = <0x2dc6c0>;
				maxim,backup-battery-output-resister = <0x64>;
			};

			regulators {
				in-ldo0-1-supply = <0x8c>;
				in-ldo7-8-supply = <0x8c>;

				sd0 {
					regulator-name = "vdd-core";
					regulator-min-microvolt = <0xf4240>;
					regulator-max-microvolt = <0x11da50>;
					regulator-boot-on;
					regulator-always-on;
					maxim,active-fps-source = <0x1>;
					regulator-init-mode = <0x2>;
					maxim,active-fps-power-up-slot = <0x1>;
					maxim,active-fps-power-down-slot = <0x6>;
					regulator-enable-ramp-delay = <0x92>;
					regulator-disable-ramp-delay = <0xff0>;
					regulator-ramp-delay = <0x6b6c>;
					regulator-ramp-delay-scale = <0x12c>;
					linux,phandle = <0xa6>;
					phandle = <0xa6>;
				};

				sd1 {
					regulator-name = "vdd-ddr-1v1";
					regulator-always-on;
					regulator-boot-on;
					regulator-init-mode = <0x2>;
					maxim,active-fps-source = <0x0>;
					maxim,active-fps-power-up-slot = <0x5>;
					maxim,active-fps-power-down-slot = <0x2>;
					regulator-min-microvolt = <0x118c30>;
					regulator-max-microvolt = <0x118c30>;
					regulator-enable-ramp-delay = <0x82>;
					regulator-disable-ramp-delay = <0x23988>;
					regulator-ramp-delay = <0x6b6c>;
					regulator-ramp-delay-scale = <0x12c>;
					linux,phandle = <0x125>;
					phandle = <0x125>;
				};

				sd2 {
					regulator-name = "vdd-pre-reg-1v35";
					regulator-min-microvolt = <0x149970>;
					regulator-max-microvolt = <0x149970>;
					regulator-always-on;
					regulator-boot-on;
					maxim,active-fps-source = <0x1>;
					maxim,active-fps-power-up-slot = <0x2>;
					maxim,active-fps-power-down-slot = <0x5>;
					regulator-enable-ramp-delay = <0xb0>;
					regulator-disable-ramp-delay = <0x7d00>;
					regulator-ramp-delay = <0x6b6c>;
					regulator-ramp-delay-scale = <0x15e>;
					linux,phandle = <0x8c>;
					phandle = <0x8c>;
				};

				sd3 {
					regulator-name = "vdd-1v8";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-always-on;
					regulator-boot-on;
					maxim,active-fps-source = <0x0>;
					regulator-init-mode = <0x2>;
					maxim,active-fps-power-up-slot = <0x3>;
					maxim,active-fps-power-down-slot = <0x4>;
					regulator-enable-ramp-delay = <0xf2>;
					regulator-disable-ramp-delay = <0x1ccf0>;
					regulator-ramp-delay = <0x6b6c>;
					regulator-ramp-delay-scale = <0x168>;
					linux,phandle = <0x3b>;
					phandle = <0x3b>;
				};

				ldo0 {
					regulator-name = "avdd-sys-1v2";
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
					regulator-boot-on;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
					regulator-enable-ramp-delay = <0x1a>;
					regulator-disable-ramp-delay = <0x272>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					linux,phandle = <0x42>;
					phandle = <0x42>;
				};

				ldo1 {
					regulator-name = "vdd-pex-1v0";
					regulator-min-microvolt = <0x100590>;
					regulator-max-microvolt = <0x100590>;
					regulator-always-on;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
					regulator-enable-ramp-delay = <0x16>;
					regulator-disable-ramp-delay = <0x276>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					linux,phandle = <0x44>;
					phandle = <0x44>;
				};

				ldo2 {
					regulator-name = "vddio-sdmmc-ap";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
					regulator-enable-ramp-delay = <0x3e>;
					regulator-disable-ramp-delay = <0x28a>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					linux,phandle = <0x9e>;
					phandle = <0x9e>;
				};

				ldo3 {
					regulator-name = "vdd-ldo3";
					regulator-min-microvolt = <0x2ab980>;
					regulator-max-microvolt = <0x2ab980>;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
					regulator-enable-ramp-delay = <0x32>;
					regulator-disable-ramp-delay = <0x456>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					status = "disabled";
					linux,phandle = <0x126>;
					phandle = <0x126>;
				};

				ldo4 {
					regulator-name = "vdd-rtc";
					regulator-min-microvolt = <0xcf850>;
					regulator-max-microvolt = <0x10c8e0>;
					regulator-always-on;
					regulator-boot-on;
					maxim,active-fps-source = <0x0>;
					maxim,active-fps-power-up-slot = <0x1>;
					maxim,active-fps-power-down-slot = <0x6>;
					regulator-enable-ramp-delay = <0x16>;
					regulator-disable-ramp-delay = <0x262>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					regulator-disable-active-discharge;
					linux,phandle = <0x127>;
					phandle = <0x127>;
				};

				ldo5 {
					regulator-name = "vdd-ldo5";
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
					regulator-enable-ramp-delay = <0x3e>;
					regulator-disable-ramp-delay = <0x280>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					status = "disabled";
					linux,phandle = <0x5c>;
					phandle = <0x5c>;
				};

				ldo6 {
					regulator-name = "vddio-sdmmc3-ap";
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-boot-on;
					maxim,active-fps-source = <0x3>;
					maxim,active-fps-power-up-slot = <0x0>;
					maxim,active-fps-power-down-slot = <0x7>;
					regulator-enable-ramp-delay = <0x24>;
					regulator-disable-ramp-delay = <0x2a2>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					linux,phandle = <0x5d>;
					phandle = <0x5d>;
				};

				ldo7 {
					regulator-name = "avdd-1v05-pll";
					regulator-min-microvolt = <0x100590>;
					regulator-max-microvolt = <0x100590>;
					regulator-always-on;
					regulator-boot-on;
					maxim,active-fps-source = <0x1>;
					maxim,active-fps-power-up-slot = <0x3>;
					maxim,active-fps-power-down-slot = <0x4>;
					regulator-enable-ramp-delay = <0x18>;
					regulator-disable-ramp-delay = <0xad0>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					linux,phandle = <0x43>;
					phandle = <0x43>;
				};

				ldo8 {
					regulator-name = "avdd-io-hdmi-dp";
					regulator-min-microvolt = <0x100590>;
					regulator-max-microvolt = <0x100590>;
					regulator-boot-on;
					regulator-always-on;
					maxim,active-fps-source = <0x1>;
					maxim,active-fps-power-up-slot = <0x6>;
					maxim,active-fps-power-down-slot = <0x1>;
					regulator-enable-ramp-delay = <0x16>;
					regulator-disable-ramp-delay = <0x488>;
					regulator-ramp-delay = <0x186a0>;
					regulator-ramp-delay-scale = <0xc8>;
					linux,phandle = <0x45>;
					phandle = <0x45>;
				};
			};

			low-battery-monitor {
				maxim,low-battery-shutdown-enable;
			};
		};
	};

If you suspect the same regulator is causing the problem, then just write a new regulator for your sdcard.

hello Wayne.

Try creating a new regulator.

There is an SD card that cannot be detected but does not give an I2C error.
Attach dmesg and device tree at this time.
What is the cause?
・dmesg(Insert SD card in 45 seconds.)
dmesg.txt (106.1 KB)
・device tree
devicetree.dts (327.0 KB)

Hello,

I just checked your dmesg/ and device-tree again with internal engineers, and their conclusion is same as my previous comment. If regulator and cd-gpios are configured fine, then the CRC error is probably due to the hardware problem.

hello Wayne.

Thank you for checking dmesg and device-tree.
I check the hardware.

hello Wayne.

The signal voltage of the SD card of the custom board was 3.3V.
When I read the TRM, it was stated that the speed mode SDR was not supported when the signal voltage was 3.3V.
So I set the device tree to remove SDR and not support 1.8V.
However, there are some SD cards that cannot be detected.
Attach dmesg, device tree and schematic.
Is there a mistake in the device tree?

・dmesg(Log that can be detected from 38 seconds, log of detection failure from 107 seconds)
dmesg.txt (70.2 KB)

・device tree
device_tree.dts (326.9 KB)

・schematic

I am not hardware guy so cannot give a true review for your schematic.

But all our previous users here are using 3.3v. Also, you use UART0_RTS as your cd-gpio, did you remember to configure the pinmux?

hello Wayne.

I’ve requested schematics from other forums and I hope they will help solve the problem.
Is there anyone who can review?

UART0_RTS configures pimux as GPIO.
Does CD-gpio need to be GPIO08?

@Trumany can you help review the schematic here?

Does CD-gpio need to be GPIO08?

No need, but just most users use that.

Hi, please refer to the SD Card Connection Example in Jetson Nano Product Design Guide in DLC. There are clear design circuits and notes included.

hello Wayne.

I used GPIO08 as cd-gpio and the result was the same.
GPIO08 pinmux consists of SDMMC3_CD.

hello Trumany.

Designed with reference to the Jetson Nano Product Design Guide.
The difference is that the resistance of CLK uses 10Ω, but it is judged that there is no problem because the maximum frequency is 50MHz or less.
I tried the CLK resistance with 0Ω and the result was the same.

Is there load switch in you design? Please read the notes carefully.

hello Trumany.

There is no load switch.
VDD is designed to be supplied at all times.
Even in the device tree, VDD is always supplied.
Do you need a load switch?
Other forums say that you don’t have to have a load switch.

The note has described very clear: The SD card supply must be enabled with a GPIO to prevent back-driving the Tegra SDMMC interface during power-on sequencing. The GPIO should have power-on reset (POR) that will ensure the supply is not enabled by default.
It might not be related to the issue you met, but it is the design request.