Cannot break on SIGFPE

I am trying to break on SIGFPE, trapping a few floating point exceptions. My process is:

  1. Enable FP exceptions with feenableexcept(FE_DIVBYZERO | FE_INVALID | FE_OVERFLOW);
  2. Using the Tegra menu, enable signals and exceptions, marking all Android exceptions (including SIGFPE)
  3. Write code that generates NaNs or divide by zero.
  4. Observe no exception is caught and the program execution continues as normal

I am building for armeabi-v7a and testing on an Android Shield tablet. Latest public TADP. SIGSEGV breaks properly for me.

My fpscr register after enabling:

fpscr = 0x20000010 s0 = 0x5f4c4453 s1 = 0x00707061 s2 = 0x5f646965 s3 = 0x74696e49 s4 = 0x5f707064 
s5 = 0x414c4453 s6 = 0x76697421 s7 = 0x5f797469 s8 = 0x00005623 s9 = 0x00000000 s10 = 0x74a635e0 
s11 = 0x74a40500 s12 = 0x00001915 s13 = 0x3f800000 s14 = 0x3f800000 s15 = 0x4588a800 s16 = 0x44e40000 
s17 = 0x3f800000 s18 = 0x3f000000 s19 = 0x3f800000 s20 = 0x00000000 s21 = 0x00000000 s22 = 0x00000000 
s23 = 0x00000000 s24 = 0x00000000 s25 = 0x00000000 s26 = 0x00000000 s27 = 0x00000000 s28 = 0x00000000 
s29 = 0x00000000 s30 = 0x00000000 s31 = 0x00000000

It seems that the hardware does not support enabling those exceptions. If everything was well, then the register value would have been 0x20000710, not 0x20000010 (i.e. the exception bits would have been set). You can read more about it here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html

Good catch. I can confirm that the fpscr register does not change when executing this code:

asm _volatile__("vmsr fpscr,%0" : :"ri" (fpscr));

 ; disassembly
 ldr r3, [r11, #-8] 
 vmsr fpscr, r3

This matter appears not to be an NVidia tooling problem.