Hi all,
I use a camera that outputs image data via the MIPI interface, my board support the camera input clock called MCLK.
When setting the MCLK frequency to 24 MHz and config the camera output size is 2516x2112 the camera output image data speed is 800Mbps/lane, my driver cannot receive the data correctly,and the driver read TEGRA_CSI_PIXEL_PARSER_STATUS register value is 0x00000034. When setting the MCLK frequency to 24 MHz and config the camera output size is 5760x4312 the camera output image data speed is 1400Mbps/lane, my driver can receive the data correctly.I think when the camera output size is 2516x2112 the TX1 parse MIPI data failed because of the MIPI CSI not not meet the corresponding timing. Does TX1 have registers to modify MIPI CSI timing? Thanks!
Hi ShaneCCC
I have modified register CSI1_PHY_CILA_CONTROL0_0 & CSI1_PHY_CILB_CONTROL0_0 value, set THS_SETTLE value form 0x05 to 0x0B( 85ns + 6 * UI < (Ths-settle-programmed + 5) * csicil_clk_period < 145ns + 10 * UI 1UI=1.25ns),
my driver can’t receive image data correctly. My BSP version is R24.2.1,but use same hardware board and TX2 the BSP version is R28.1 can receive date correctly. Any difference between TX1 and TX2 ?
Do you mean the same REG setting(resolution) can work on TX2 but not TX1? This shouldn’t be happened if all things are correct. Did you use v4l2-ctl to get frame data? I am confuse with your first and this comment.
Yes, the same REG setting(resolution) can work on TX2 but not TX1. I do not use v4l2-ctl to get frame data, I use my application get frame data.
Try modify the discontinuous_clk first. If still have problem try the cil_settletime. My early comment to adjust the timing is for v4l2-ctl.
discontinuous_clk = "no";
dpcm_enable = "false";
cil_settletime = "0";
Hi ShaneCCC,
Modify these in dbs file? Which file use the these properties ?
Yes, device tree file in your sensor driver dts file.
The reference sensor is tegra210-camera-e3323-a00.dtsi
But no c file use these properties in R24.2.1 bsp version.