Cannot set UPHY Lane 0 PCIe config in pinmux

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
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1

I asked a similar question before when JP5 was still only early access.
I am trying to use PCIe C0, on UPHY lane 0 which is normally set to USB 3.2. I can change the UPHY mode in the pinmux just fine but the sideband signals are not available. Refclk and PERST/CLKREQ cannot be set in the pinmux, even though it is listed as supported in the design guide.

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Will this be added at a later date? I would like all of my mPCIe slots to work.

3

We will support those uphy configuration mentioned in design guide after 5.0GA.

5

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