Can't access to SPI controller registers on Tegra TK1

Hi, I have an issue concerning the SPI Controller Register on the Jetson TK1.

I have followed this tuto about how to build and flash U-boot:
Now I would like to access to the SPI Controller Registers via my serial connexion and the terminal.

I have already made some test about on other Registers. I can Display and modify them with the “md” and “mw” commands, but when I try to display the address from 0x7000d000 to 0x7000de00 (I2c4 to SPI 2B-6 in the documentation) the terminal seems to crash (it Displays: “7000de00:” and I can’t do anything else).

I first thought that it was an issue of initialization. I have then try to initialize the CLK_RST_CONTROLLER_OUT_END_H_0 register to enable the SPI1, and then the CLK_SOURCE_SPI1_0 with different clock sources but no change.

Furthermore, it seems that I can’t access to other addresses like 0x70006000 (UART-A). I don’t even understand where is the problem from?

I can verify lockup when reading 0x7000de000. I have a JTAG debugger, but OpenOCD does not work with this board…I have only the beginnings of config files for this. Should even minimal OpenOCD support be added, JTAG would tell us much more.

Just an observation…md displays memory as 16 rows of data, 16 bytes per row. So starting at 0x7000d000, the next row shows from 0x7000d010, and the next 0x7000d020, so on.

As an experiment, I began displaying 0x7000d000 and then again at every 16 bytes, and found the first row where lockup failure would occur was only the very next 16 byte row added by incrementing to “md 0x7000d010”.

I wanted to see what happened if I displayed only a single byte further beyond 0x7000d000 (does not align with the 16 byte boundaries…u-boot probably is not set up for random boundaries), and I got a data abort:

Tegra124 (Jetson TK1) # md 0x7000d001
7000d001:data abort
pc : [<ffe7e774>]	   lr : [<ffe7e760>]
sp : ffa4e688  ip : 00000000	 fp : 7000d001
r10: 00000004  r9 : ffa51f04	 r8 : 7000d001
r7 : 00000040  r6 : 00000000	 r5 : 00000004  r4 : 00000004
r3 : 00000001  r2 : 00000001	 r1 : 0000003a  r0 : 00000009
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

U-Boot SPL 2014.04-rc2 (Jun 18 2014 - 11:16:32)

Not much to go by. Just food for thought, I’m thinking that the documentation for register addresses in the TegraK1 TRM do not take into account the PM375 board it is attached to, and that perhaps some pinmux and memory controller setup at this stage, combined with physical pin wiring, make the SPI you are looking for unavailable.

Thank you for your answer. I’m still working on it but I have no Solutions for now. If somebody has an idea, feel free to share it!