Can't use can_gpio2_paa2 or can_gpio2_paa3 as open-drain output?

We want to use pin can_gpio2_paa2 (Jetson signal GPIO9/MOTION_INT) and can_gpio2_paa3 (Jetson signal CAN1_ERR) as open-drain outputs, so we added the following pinmux definitions to the device tree

can_gpio2_paa2 {
			nvidia,pins = "can_gpio2_paa2";
			nvidia,function = "rsvd1";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

	can_gpio3_paa3 {
			nvidia,pins = "can_gpio3_paa3";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			nvidia,tristate = <TEGRA_PIN_DISABLE>;
			nvidia,enable-input = <TEGRA_PIN_DISABLE>;
			nvidia,open-drain = <TEGRA_PIN_ENABLE>;
	};

But we got this error during boot:

[    0.722449] tegra186-pinctrl 2430000.pinmux: Config param 0003 (nvidia,open-drain) not supported on group can_gpio2_paa2
[    0.733811] tegra186-pinctrl 2430000.pinmux: pin_config_group_set op failed for group 26
[    0.742263] tegra186-pinctrl 2430000.pinmux: Error applying setting, reverse things back
[    0.750733] tegra186-pinctrl 2430000.pinmux: failed to select default state

It seems the OD field of both pins is prohibited in the pinmux driver t18x/drivers/pinctrl/pinctrl-tegra186.c (flagged with value -1 between value ‘10’ and ‘12’) shown below,

PINGROUP(can_gpio2_paa2,        GPIO,        RSVD1,        RSVD2,        RSVD3,        0x3038,        1,        Y,      -1,    6,    -1,    9,    10,    -1,    12,    Y,    -1,    -1,    Y),
PINGROUP(can_gpio3_paa3,        RSVD0,        RSVD1,        RSVD2,        RSVD3,        0x3040,        1,        Y,     -1,    6,    -1,    9,    10,    -1,    12,    Y,    -1,    -1,    Y),

The TX2 datasheet didn’t seem to mention OD is disallowed when these pins are used as GPIO. Could you please confirm if it’s the case or just a software bug? Thanks.

hello rong1129,

according to the attachment, only MPIO pad type are DD or DP_AUX could configure as open-drain.
since these 2 pins can_gpio2_paa2 (Jetson signal GPIO9/MOTION_INT) and can_gpio2_paa3 (Jetson signal CAN1_ERR) pad type is CZ. they’re not able to configure as open-drain.

mpio_types.JPG

Is there any plan to update the pinmux spreadsheet to reflect this?

Also, what document is that table in?

hello brad_,

please download the Parker Series SoC Technical Reference Manual at Embedded Download Center.
you should able to find the table 57. MPIO Pad Types in the chapter 8.3 MPIO Pad and Brick Description
thanks