Carrier Board Design With External Emmc

seymoura · May 12, 2023, 3:57pm

I copied the contents from 3460000 to 3440000 in the dtsi so that they are similar the exact code is below:

sdhci_emmc: sdhci@3460000 {
	uhs-mask = <0x0>;
	nvidia,enable-hwcq;
	status = "okay";
};
sdmmc3: sdhci@3440000 {
	uhs-mask = <0x0>;
	nvidia,enable-hwcq;
	status = "okay";
};

WayneWWW · May 12, 2023, 4:00pm

No, that was not what I meant…

I mean the porting from these two. Not just 3 lines matching…

seymoura · May 12, 2023, 5:02pm

Below is the updated code from .dts

sdhci@3460000 {
		compatible = "nvidia,tegra194-sdhci";
		reg = <0x0 0x3460000 0x0 0x20000>;
		interrupts = <0x0 0x41 0x4>;
		iommus = <0x2 0x17>;
		dma-coherent;
		max-clk-limit = <0xbebc200>;
		ddr-clk-limit = <0x30a32c0>;
		bus-width = <0x8>;
		only-1-8-v;
		ignore-pm-notify;
		keep-power-in-suspend;
		non-removable;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		mmc-hs400-1_8v;
		mmc-hs400-enhanced-strobe;
		nvidia,min-tap-delay = <0x60>;
		nvidia,max-tap-delay = <0x8b>;
		nvidia,en-periodic-cflush;
		nvidia,periodic-cflush-to = <0xa>;
		resets = <0x5 0x55>;
		reset-names = "sdhci";
		pll_source = "pll_p", "pll_c4_out0_lj";
		nvidia,set-parent-clk;
		nvidia,parent_clk_list = "pll_p", "pll_p", "NULL", "NULL", "NULL", "NULL", "NULL", "NULL", "pll_p", "pll_c4_out0_lj", "pll_c4_out0_lj";
		clocks = <0x4 0x7b 0x4 0x66 0x4 0xed 0x4 0xdb>;
		clock-names = "sdmmc", "pll_p", "pll_c4_out0_lj", "sdmmc_legacy_tm";
		status = "okay";
		vmmc-supply = <0x1b>;
		vqmmc-supply = <0x18>;
		uhs-mask = <0x0>;
		nvidia,enable-hwcq;
		linux,phandle = <0xbf>;
		phandle = <0xbf>;

		prod-settings {
			#prod-cells = <0x4>;

			prod {
				prod = <0x0 0x4 0xfff 0x200 0x0 0x28 0x20 0x20 0x0 0x100 0x1fff004a 0x14080000 0x0 0x10c 0x3f00 0x2800 0x0 0x128 0x43000000 0x0 0x0 0x1ac 0x4 0x0 0x0 0x1c0 0x1fc0 0x40 0x0 0x1c4 0x3ff77 0x400 0x0 0x1e0 0x87f7f000 0xa0a000 0x0 0x1e4 0x20000000 0x20000000 0x0 0x204 0x80000000 0x0 0x0 0x218 0x80000000 0x0>;
			};

			prod_c_ds {
				prod = <0x0 0x100 0x1fff0000 0x14080000>;
			};

			prod_c_hs {
				prod = <0x0 0x100 0x1fff0000 0x14080000>;
			};

			prod_c_cqe {
				prod = <0x0 0xf008 0x1 0x1>;
			};

			prod_c_ddr52 {
				prod = <0x0 0x3c 0x70000 0x40000 0x0 0x120 0xfffe 0x298>;
			};

			prod_c_hs200 {
				prod = <0x0 0x3c 0x70000 0x30000 0x0 0x1c0 0xe000 0x4000>;
			};

			prod_c_hs400 {
				prod = <0x0 0x3c 0x70000 0x50000 0x0 0x100 0xff0008 0x80008 0x0 0x1c0 0xe000 0x4000 0x0 0x1e4 0x7f7f 0x0>;
			};

			prod_c_sdr50 {
				prod = <0x0 0x3c 0x70000 0x20000>;
			};
		};
	};

	sdhci@3440000 {
		compatible = "nvidia,tegra194-sdhci";
		reg = <0x0 0x3440000 0x0 0x20000>;
		interrupts = <0x0 0x40 0x4>;
		iommus = <0x2 0x18>;
		dma-coherent;
		max-clk-limit = <0xc65d400>;
		bus-width = <0x4>;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		sd-uhs-sdr104;
		sd-uhs-sdr50;
		sd-uhs-sdr25;
		sd-uhs-sdr12;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		cd-inverted;
		nvidia,min-tap-delay = <0x60>;
		nvidia,max-tap-delay = <0x8b>;
		nvidia,vqmmc-always-on;
		pwrdet-support;
		pinctrl-names = "sdmmc_e_33v_enable", "sdmmc_e_33v_disable";
		pinctrl-0 = <0x1c>;
		pinctrl-1 = <0x1d>;
		ignore-pm-notify;
		resets = <0x5 0x54>;
		reset-names = "sdhci";
		pll_source = "pll_p", "pll_c4_muxed";
		nvidia,set-parent-clk;
		nvidia,parent_clk_list = "pll_p", "pll_p", "pll_p", "pll_p", "pll_p", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "pll_c4_muxed", "NULL";
		clocks = <0x4 0x7a 0x4 0x66 0x4 0xf1 0x4 0xdb>;
		clock-names = "sdmmc", "pll_p", "pll_c4_muxed", "sdmmc_legacy_tm";
		uhs-mask = <0x0>;
		nvidia,en-periodic-calib;
		status = "okay";
		nvidia,enable-hwcq;
		test-value = "testing123";
		linux,phandle = <0xf0>;
		phandle = <0xf0>;

		prod-settings {
			#prod-cells = <0x4>;

			prod_c_1_8v {
				prod = <0x0 0x1e0 0x7f00000 0x600000>;
			};

			prod_c_3_3v {
				prod = <0x0 0x1e0 0x7f00000 0x800000>;
			};

			prod {
				prod = <0x0 0x4 0xfff 0x200 0x0 0x28 0x22 0x2 0x0 0x100 0x1fff004a 0x5090000 0x0 0x128 0x42000000 0x0 0x0 0x1ac 0x4 0x0 0x0 0x1c0 0x1fc0 0x40 0x0 0x1c4 0x3ff77 0x400 0x0 0x1e0 0x8007f000 0x7000 0x0 0x1e4 0x20000000 0x20000000 0x0 0x204 0x80000000 0x0>;
			};

			prod_c_ds {
				prod = <0x0 0x100 0x1fff0000 0x5090000>;
			};

			prod_c_hs {
				prod = <0x0 0x100 0x1fff0000 0x5090000>;
			};

			prod_c_ddr52 {
				prod = <0x0 0x3c 0x70000 0x40000 0x0 0x120 0xfffe 0x298>;
			};

			prod_c_hs200 {
				prod = <0x0 0x3c 0x70000 0x30000 0x0 0x1c0 0xe000 0x4000>;
			};

			prod_c_sdr104 {
				prod = <0x0 0x3c 0x70000 0x30000 0x0 0x1c0 0xe000 0x4000>;
			};

			prod_c_sdr12 {
				prod = <0x0 0x3c 0x70000 0x0>;
			};

			prod_c_sdr25 {
				prod = <0x0 0x3c 0x70000 0x10000>;
			};

			prod_c_sdr50 {
				prod = <0x0 0x3c 0x70000 0x20000 0x0 0x1c0 0xe000 0x8000>;
			};
		};
	};

WayneWWW · May 13, 2023, 3:21am

Hi,

I hope you didn’t put my previous comment in the wrong way.

You only need to port those missing items from sdmmc4 to sdmmc3. For some values that you should never change. For example, clock/clock-names/pll sources/reset…etc.

seymoura · May 15, 2023, 1:08pm

Morning! Ok well good news and sorta not. I rebooted the changes with some that I made from your last comment and now our system is in an endless boot cycle. Maby the emmc was picked up and its trying to boot from it?

Below is the dts of @346 and @344 along with the endless log that I had when booting. I tried to capture everything as best as I could. Hope this helps.

sdhci@3460000 {
compatible = “nvidia,tegra194-sdhci”;
reg = <0x00 0x3460000 0x00 0x20000>;
interrupts = <0x00 0x41 0x04>;
iommus = <0x02 0x17>;
dma-coherent;
max-clk-limit = <0xbebc200>;
ddr-clk-limit = <0x30a32c0>;
bus-width = <0x08>;
only-1-8-v;
ignore-pm-notify;
keep-power-in-suspend;
non-removable;
cap-mmc-highspeed;
cap-sd-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
nvidia,min-tap-delay = <0x60>;
nvidia,max-tap-delay = <0x8b>;
nvidia,en-periodic-cflush;
nvidia,periodic-cflush-to = <0x0a>;
resets = <0x05 0x55>;
reset-names = “sdhci”;
pll_source = “pll_p\0pll_c4_out0_lj”;
nvidia,set-parent-clk;
nvidia,parent_clk_list = “pll_p\0pll_p\0NULL\0NULL\0NULL\0NULL\0NULL\0NULL\0pll_p\0pll_c4_out0_lj\0pll_c4_out0_lj”;
clocks = <0x04 0x7b 0x04 0x66 0x04 0xed 0x04 0xdb>;
clock-names = “sdmmc\0pll_p\0pll_c4_out0_lj\0sdmmc_legacy_tm”;
status = “okay”;
vmmc-supply = <0x1b>;
vqmmc-supply = <0x18>;
uhs-mask = <0x00>;
nvidia,enable-hwcq;
linux,phandle = <0xbf>;
phandle = <0xbf>;
  prod-settings {
  	#prod-cells = <0x04>;

  	prod {
  		prod = <0x00 0x04 0xfff 0x200 0x00 0x28 0x20 0x20 0x00 0x100 0x1fff004a 0x14080000 0x00 0x10c 0x3f00 0x2800 0x00 0x128 0x43000000 0x00 0x00 0x1ac 0x04 0x00 0x00 0x1c0 0x1fc0 0x40 0x00 0x1c4 0x3ff77 0x400 0x00 0x1e0 0x87f7f000 0xa0a000 0x00 0x1e4 0x20000000 0x20000000 0x00 0x204 0x80000000 0x00 0x00 0x218 0x80000000 0x00>;
  	};

  	prod_c_ds {
  		prod = <0x00 0x100 0x1fff0000 0x14080000>;
  	};

  	prod_c_hs {
  		prod = <0x00 0x100 0x1fff0000 0x14080000>;
  	};

  	prod_c_cqe {
  		prod = <0x00 0xf008 0x01 0x01>;
  	};

  	prod_c_ddr52 {
  		prod = <0x00 0x3c 0x70000 0x40000 0x00 0x120 0xfffe 0x298>;
  	};

  	prod_c_hs200 {
  		prod = <0x00 0x3c 0x70000 0x30000 0x00 0x1c0 0xe000 0x4000>;
  	};

  	prod_c_hs400 {
  		prod = <0x00 0x3c 0x70000 0x50000 0x00 0x100 0xff0008 0x80008 0x00 0x1c0 0xe000 0x4000 0x00 0x1e4 0x7f7f 0x00>;
  	};

  	prod_c_sdr50 {
  		prod = <0x00 0x3c 0x70000 0x20000>;
  	};
  };
};

sdhci@3440000 {
compatible = “nvidia,tegra194-sdhci”;
reg = <0x00 0x3440000 0x00 0x20000>;
interrupts = <0x00 0x40 0x04>;
iommus = <0x02 0x18>;
dma-coherent;
max-clk-limit = <0xc65d400>;
bus-width = <0x04>;
cap-mmc-highspeed;
cap-sd-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
nvidia,min-tap-delay = <0x60>;
nvidia,max-tap-delay = <0x8b>;
nvidia,en-periodic-cflush;
nvidia,periodic-cflush-to = <0x0a>;
resets = <0x05 0x54>;
reset-names = “sdhci”;
pll_source = “pll_p\0pll_c4_muxed”;
nvidia,set-parent-clk;
nvidia,parent_clk_list = “pll_p\0pll_p\0pll_p\0pll_p\0pll_p\0pll_c4_muxed\0pll_c4_muxed\0pll_c4_muxed\0pll_c4_muxed\0pll_c4_muxed\0NULL”;
clocks = <0x04 0x7a 0x04 0x66 0x04 0xf1 0x04 0xdb>;
clock-names = “sdmmc\0pll_p\0pll_c4_muxed\0sdmmc_legacy_tm”;
uhs-mask = <0x00>;
status = “okay”;
nvidia,enable-hwcq;
linux,phandle = <0xf0>;
phandle = <0xf0>;
  prod-settings {
  	#prod-cells = <0x04>;

  	prod {
  		prod = <0x00 0x04 0xfff 0x200 0x00 0x28 0x20 0x20 0x00 0x100 0x1fff004a 0x14080000 0x00 0x10c 0x3f00 0x2800 0x00 0x128 0x43000000 0x00 0x00 0x1ac 0x04 0x00 0x00 0x1c0 0x1fc0 0x40 0x00 0x1c4 0x3ff77 0x400 0x00 0x1e0 0x87f7f000 0xa0a000 0x00 0x1e4 0x20000000 0x20000000 0x00 0x204 0x80000000 0x00 0x00 0x218 0x80000000 0x00>;
  	};

  	prod_c_ds {
  		prod = <0x00 0x100 0x1fff0000 0x14080000>;
  	};

  	prod_c_hs {
  		prod = <0x00 0x100 0x1fff0000 0x14080000>;
  	};

  	prod_c_cqe {
  		prod = <0x00 0xf008 0x01 0x01>;
  	};

  	prod_c_ddr52 {
  		prod = <0x00 0x3c 0x70000 0x40000 0x00 0x120 0xfffe 0x298>;
  	};

  	prod_c_hs200 {
  		prod = <0x00 0x3c 0x70000 0x30000 0x00 0x1c0 0xe000 0x4000>;
  	};

  	prod_c_hs400 {
  		prod = <0x00 0x3c 0x70000 0x50000 0x00 0x100 0xff0008 0x80008 0x00 0x1c0 0xe000 0x4000 0x00 0x1e4 0x7f7f 0x00>;
  	};

  	prod_c_sdr50 {
  		prod = <0x00 0x3c 0x70000 0x20000>;
  	};
  };
};

LOG_V5.txt (200.7 KB)

seymoura · May 15, 2023, 1:36pm

Ok I tried fixing the boot order in cboot and that did not fix the issue

WayneWWW · May 15, 2023, 2:15pm

Sorry, I am just not sure what is your criteria here to add things.

For example, mmc4 has something like “only-1-8-v” and “non-removable”. Why you still not added them after this conversation so far?
Not sure what did you do here.

Also, what is your hardware schematic? You also need to indicate vmmc-supply and vqmmc-supply according to your hardware design.

seymoura · May 15, 2023, 2:35pm

Hey!

As for not adding those attributes its because I’m not sure what to add and that I have never done this before, thus I would not know what to add.

As for the hardware schematic I can write it out because its fairly simple:

PIN 219: SDMMC_DATA0
PIN 221: SDMMC_DATA1
PIN 223: SDMMC_DATA2
PIN 225: SDMMC_DATA3
PIN 227: SDMMC_CMD
PIN 229: SDMMC_CLK

PIN 206: GPIO7_PWR_CIRCUIT (OUTPUT pin)
When this is turned on 3.3v is applied to the emmc to supply power

PIN 208: GPIO8_SDMMC_CD (INPUT pin)
When gpio7 is high it will input 1.8v to the pin for input

Should I add those attributes that you mentioned previously even when my device is operating off of 3.3 volts?

Hope this clears things up.

Trumany · May 16, 2023, 2:29am

Can you share your schematic of this part? Looks like some points are not clear such as the power supply of 3.3v/1.8v.

seymoura · May 16, 2023, 1:40pm

Sent message

seymoura · May 17, 2023, 12:22pm

Ended up fixing the issue ourselves. Enabling our custom power circuit on boot and setting the params base with dtc fixed the issues we where having. Device shows on lsblk.

system · June 7, 2023, 12:55am

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Carrier Board Design With External Emmc

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