CBoot - Problem with setting the LCD0_BKLT_PWM pin

Hello
In CBoot I would like to set the LCD0_BKLT_PWM pin to high after my display panel has initialized.
Here my code:

struct gpio_driver *gpio_drv;
tegrabl_gpio_driver_get(TEGRA_GPIO_AON_CHIPID, &gpio_drv);
gpio_config(gpio_drv, 8, GPIO_PINMODE_OUTPUT);
gpio_write(gpio_drv,8, GPIO_PIN_STATE_HIGH);

According to the Jetson-TX2-Generic-Customer-Pinmux-Template_v1.xx.xlsm the LCD0_BKLT_PWM is pin PU.00 (which would have the pin number 8) and inherents to the AON GPIO. The problem ist that i can’t set this GPIO to high. I can set any other pin of the tegra main gpio but not the LCD0_BKLT_PWM from the aon gpio. I have also tried to set the register pinmux.0x0c301080 = 0x00000400; in my BCT cfg file but without success. Is there any thing which I have to consider or is there a bug in the tegra_gpio_aon_driver.

hello Werner1,

I would like to know your environment setups.
for example,
which JetPack release you’re working with.
are you able to have uart serial console connected for checking bootloader logs?

Hello Jerry,
I’m using a display which is connected to a EDP-2-LVDS translator. This translator works fine with cboot to show up a boot screen. The CBoot version is from R28.2.1.
I’m setting two pins (1st: LCD0_BKLT_PWM PU.00, 2nd: LCD_VDD_EN, PP.03) in a row:

struct gpio_driver *gpio_main_drv, *gpio_aon_drv;
tegrabl_gpio_driver_get(TEGRA_GPIO_MAIN_CHIPID, &gpio_main_drv);
tegrabl_gpio_driver_get(TEGRA_GPIO_AON_CHIPID, &gpio_aon_drv);
gpio_config(gpio_aon_drv, 8, GPIO_PINMODE_OUTPUT);
gpio_config(gpio_main_drv, 123, GPIO_PINMODE_OUTPUT);
gpio_write(gpio_aon_drv, 8, GPIO_PIN_STATE_HIGH);
gpio_write(gpio_main_drv, 123, GPIO_PIN_STATE_HIGH);

Here the resulting log:

[0002.483] I> gpio framework initialized
[0002.487] I> tegrabl_gpio_driver_register: register 'tegra_gpio_main_driver' driver
[0002.494] D> tegrabl_gpio_driver_init: tegra gpio driver:tegra_gpio_main_driver registered successfully
[0002.504] D> Found gpio driver 'tegra_gpio_main_driver' in list
[0002.509] I> tegrabl_gpio_driver_register: register 'tegra_gpio_aon_driver' driver
[0002.517] D> tegrabl_gpio_driver_init: tegra gpio driver:tegra_gpio_aon_driver registered successfully
[0002.526] I> tegrabl_tca9539_init: i2c bus: 0, slave addr: 0xee
...
[0002.929] E> tca9539_device_init: failed to write polar reg
[0002.934] E> tegrabl_tca9539_init: failed to init device!
[0002.939] E> GPIO TCA9539 driver init failed
...
[0003.678] I> tegrabl_gpio_driver_register: register 'max77620-gpio' driver
...
[0009.851] I> dp lt: CE done
[0009.853] D> dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[0009.862] D> Found gpio driver 'max77620-gpio' in list
[0009.867] D> Found gpio driver 'tegra_gpio_aon_driver' in list
[0009.872] D> Found gpio driver 'tegra_gpio_main_driver' in list
[0009.878] D> Found gpio driver 'max77620-gpio' in list
[0009.883] D> Found gpio driver 'tegra_gpio_aon_driver' in list
[0009.894] D> DP enable successful

I can set the LCD_VDD_EN gpio but not the LCD0_BKLT_PWM.

By the way: how can the LCD0_BKLT_PWM be configured PWM output in cboot? Can I forward the SOR_NV_PDISP_SOR_PWM_CTL_0 to this pin?

Hello Jerry, do you have any news for me?

Have you ever enabled any other GPIO pin that is from AON controller?

I have successfully tried to set another GPIO from the AON bank (e.g. GPIO4_CAM_STROBE). Could this be a problem with my pinmux setttings for the LCD0_BKLT_PWM pin? How can I configure LCD0_BKLT_PWM to set this pin to high or configure this to pwm output in cboot?

I would like to enable the PWM with 100% duty for the LCD0_BKLT_PWM pin ether in CBoot or in U-Boot. According to the TRM I need to set the PWM_CONTROLLER_PWM_CSR_0_x register to 0x81000000 (enable the pwm modulator and set the bit 24 to 1).
But when I set this value in U-Boot nothing happens. When I try to read the register afterwards I get following:

Tegra186 (P2771-0000-500) # md.w 0x3280000
03280000: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280010: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280020: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280030: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280040: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280050: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280060: 1009 dead 1009 dead 1009 dead 1009 dead    ................
03280070: 1009 dead 1009 dead 1009 dead 1009 dead    ................

Referencing to this topic https://devtalk.nvidia.com/default/topic/1023890/jetson-tx2/writing-to-peripheral-register-from-uboot-using-mw-command-fails-in-tx2/ the pwm unit seems to be ether in reset or disabled. Which register must be set to enable the pwm unit in the U-Boot?

@Werner1 I had this similar issue, but not on U-Boot. This occurs when the hardware module is being held in reset and its clock isn’t enabled. Now, here’s the tricky part. From reading the TRM you might imagine that all you need to do is write to the clock-and-reset (CAR) registers defined for the I2C module you want to enable (See Chapter 4 on the Clock Controller). HOWEVER, these registers are not able to be accessed from the CCPLEX; instead, only the BPMP coprocessor can access these registers. This isn’t well documented, and the protocol for communicating with the BPMP isn’t well documented either; it’s called Tegra IVC.

The current source of U-Boot for the TX2 has support for BPMP communication, so if you need to re-implement it, look there. This also probably means that the latest release of U-Boot for TX2 has support for enabling the device you needed.