Change De-emphasis level for PCIe in NVIDIA Jetson Xavier NX

Hi there,
Is it possible to change the de-emphasis level on Nvidia Jetson Xavier NX?
I tried changing the kernel source and edited the pcie-tegra.c file to change the de-emp level inside tegra_pcie_dw_host_init() function. Till the end of the function the 20th bit, which is for SEL_DEEMPHASIS (if I am not wrong), in PORT_LOGIC_GEN2_CTRL remains 1.
But somehow, in lspci -vvv output, it stays at -6 dB.
I have looked at other posts, but it doesn’t clarify my doubts.
Kernel version: 4.9.253-tegra

Could you please give the snippet of your code to show how it is changed?

pcie-tegra-de-emphasis-edit.c (9.3 KB)
Sure, I have attached the c file containing the changes I made in tegra_pcie_dw_host_init().

The SEL_DEEMPHASIS has been defined like this.
#define SEL_DEEMPHASIS BIT(20)

The boot logs shows
[ 6.177429] tegra-pcie-dw 141a0000.pcie: -------->>> Inside tegra_pcie_dw_host_init <<<<-----------
[ 6.177615] tegra-pcie-dw 141a0000.pcie: SEL_DEEMPHASIS: 1048576
[ 6.177717] tegra-pcie-dw 141a0000.pcie: PORT_LOGIC_GEN2_CTRL #1: 0x10820
[ 6.177829] tegra-pcie-dw 141a0000.pcie: PORT_LOGIC_GEN2_CTRL #2: 0x10820
[ 6.177978] tegra-pcie-dw 141a0000.pcie: PORT_LOGIC_GEN2_CTRL #3: 0x110820
[ 6.286048] tegra-pcie-dw 141a0000.pcie: link is up
[ 6.286194] tegra-pcie-dw 141a0000.pcie: PORT_LOGIC_GEN2_CTRL #END: 1116212

Thank you!

Hi,
Any update?
Thanks

Hi,

Along with SEL_DEEMPHASIS you have to set desired value in PCIE_CAP_COMPLIANCE_PRESET.
Refer to How to change to pcie de-emphasis for some more details.

Thanks,
Manikanta

Hi,

Thanks for the reply!
I cannot understand from the post that which value should be set in PCIE_CAP_COMPLIANCE_PRESET. I tried changing the value (1,2 and 15) just before changing SEL_DEEMPHASIS, but it has no effect.
In that post, it says that NVMe drive requests it.
We have FPGA connected as an endpoint device. In this case FPGA also has to be programmed to set the de-emphasis value?

Thanks,
Meet

Hi,

  1. Set DBI_RO_WR_EN=1 in register RC_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_0.

  2. For Gen2, set PCIE_CAP_SEL_DEEMPHASIS=1b in register RC_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_0 for -3.5dB de-emphasis.

  3. For Gen3, set PCIE_CAP_COMPLIANCE_PRESET=0001b in register RC_PF0_PCIE_CAP_LINK_CONTROL2_LINK_STATUS2_REG_0 for -3.5dB de-emphasis.

  4. Clear DBI_RO_WR_EN=0 in register RC_PF0_PORT_LOGIC_MISC_CONTROL_1_OFF_0.

Add this code at the same place you are modifying now.

Thanks,
Manikanta

Hi Manikanta,

Thank you so much for detailed steps.
The Current De-emphasis Level has been set to -3.5dB. I can see in lspci -vvv 's output.

Regards,
Meet

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