Change PWM to use PLLAON as clock source

Hi,

we are trying to enable PLLAON on Jetpack 4.6 to achieve more accuracy of the PWM signal (GPIO) according to the documentation.

We already managed to enable PLLAON for CAN, but we are not able to get it working for PWM, because we are missing detailed steps on what to do i.e. what to change in which device tree file.

hello user53022,

that’s pre-built binary file without sources, you’ll need to convert BPMPFW-DTB to modify the settings;
the later configuration to modify the DTS is available via Jetson Linux | NVIDIA Developer, please download the L4T Driver Package (BSP) Sources.
thanks

Hello JerryChang,

thank you for your reply.

To clarify my question a little bit more. I used to use Jetpack version 4.3 which works fine for controlling an electric motor via pwm4, because pwm4 had pll_aon as parent as you can see in fileclk_tree_jetpack_4_3_old.txt (29.6 KB)
In Jetpack version 4.6 the pwm signal differs by approx 1 Hz compared to the old Jetpack 4.3 version. The accuracy difference is enough to make the electric motor controlled via pwm4 behave differently. We managed to get CAN to have parent pll_aon as parent as you can see in clk_tree_jetpack_4_6_current.txt (29.6 KB), by the steps descripted in documentation. But in my Jetpack 4.6 clock tree pwm4 has still pllp_aon as a parent as you can also see in clk_tree_jetpack_4_6_current.txt (29.6 KB)

I downloaded the [quote=“JerryChang, post:3, topic:195688”]
L4T Driver Package (BSP) Sources
[/quote] package and i am able to build it according to documentation.

Now i’m a little lost. What do i have to change to get CAN and PWM4 to have PLLAON as parent as it used to be in Jetpack 4.3?

hello user53022,

could you please modify the device tree sources as following, to add pllaon to the list in clock-names for PWM4.
for example,

diff --git a/kernel-dts/tegra194-soc/tegra194-soc-pwm.dtsi b/kernel-dts/tegra194-soc/tegra194-soc-pwm.dtsi
@@ -57,8 +57,9 @@
                compatible = "nvidia,tegra194-pwm";
                reg = <0x0 0xc340000 0x0 0x10000>;
                nvidia,hw-instance-id = <0x3>;
-               clocks = <&bpmp_clks TEGRA194_CLK_PWM4>;
-               clock-names = "pwm";
+               clocks = <&bpmp_clks TEGRA194_CLK_PWM4>,
+                       <&bpmp_clks TEGRA194_CLK_PLLAON>;
+               clock-names = "pwm", "pllaon";

Hello JerryChang,

i made the changes you proposed to tegra194-soc-pwm.dtsi. I build it and then I was not sure how to flash the change to the jetson. What i did:

  1. I copied tegra194-p3668-all-p3509–0000.dtb to the nvidia sdk:
cp kernel_out/arch/arm64/boot/dts/tegra194-p3668-all-p3509-0000.dtb ~/nvidia/nvidia_sdk/JetPack_4.6_Linux_JETSON_AGX_XAVIER_TARGETS/Linux_for_Tegra/kernel/dtb/
  1. sudo ./flash.sh -r -k kernel-dtb jetson-xavier nvme0n1p1

That had no effect.

I checked the old Jetpack 4.3 /boot/tegra194-p2888-0001-p2822-0000.dtb file on the jetson. The entry for pwm4 is:

        pwm@c340000 {
                compatible = "nvidia,tegra194-pwm";
                reg = <0x0 0xc340000 0x0 0x10000>;
                nvidia,hw-instance-id = <0x3>;
                clocks = <0x4 0x6c>;
                clock-names = "pwm";
                #pwm-cells = <0x2>;
                resets = <0x5 0x47>;
                reset-names = "pwm";
                status = "okay";
                linux,phandle = <0x14d>;
                phandle = <0x14d>;
        };

In contrast to your suggested changes, there’s no pllaon added to clock-names and 0x4 0x5e is missing from clocks, but in the clk_tree pwm4 has pll_aon as parent. So there has to be another way to make pll_aon the parent of pwm4.