change resolution eDp?

How do you do change eDp resolution?

This procedure is performed with power on.

edid change(1920x1080 3840x2160 …) -> link training ok -> xrandr and fbset -> change fail

Hi ChiHong,

Do you mean modifying the EDID data in EEPROM and then reboot??

Could you provide your method that I can reproduce this problem on my devices?

Hi,

I hack the edid data and change the resolution to 3840x2160.

However, my xrandr and fbset work.

1.xrandr
Screen 0: minimum 8 x 8, current 7680 x 2160, maximum 16384 x 16384
DP-0 connected primary 3840x2160+0+0 (normal left inverted right x axis y axi mm
3840x2160 60.01*+
HDMI-0 connected 3840x2160+3840+0 (normal left inverted right x axis y axis)
3840x2160 30.00*+ 29.97 25.00 24.00 23.98
2560x1440 59.96
1920x1080 60.00 59.95 30.00 29.97 61.25
1600x900 60.00
1280x1024 60.00
1280x800 59.81
1280x720 60.00 59.94
1152x864 59.97
1024x768 60.01
800x600 60.32
720x480 59.94
640x480 59.94 59.94

2.xrandr --output DP-0 --off

3.eDP panel edid change -> 1920x1080

4.panel HPD ON/OFF

5.xrandr --output DP-0 --auto

6.xrandr
Screen 0: minimum 8 x 8, current 7680 x 2160, maximum 16384 x 16384
DP-0 connected primary 3840x2160+0+0 (normal left inverted right x axis y axi mm
3840x2160 60.01*+
HDMI-0 connected 3840x2160+3840+0 (normal left inverted right x axis y axis)
3840x2160 30.00*+ 29.97 25.00 24.00 23.98
2560x1440 59.96
1920x1080 60.00 59.95 30.00 29.97 61.25
1600x900 60.00
1280x1024 60.00
1280x800 59.81
1280x720 60.00 59.94
1152x864 59.97
1024x768 60.01
800x600 60.32
720x480 59.94
640x480 59.94 59.94

HPD is not supported on my panel.

Could you take a look at kernel code

/kernel/drivers/video/tegra/dc/dp.c

and check if this function is called again after hpd?

tegra_edp_edid_read(dp)

Is there any method to edid read forcibly? I would like to know

Currently, it seems no such method in kernel. edid read is only called when panel enable.

You may need to modify the driver code yourself.

Resolution has been changed by code revision.

1.eDP panel edid 1920x1080
2.eDP panel edid change -> 3840x2160
3.change ok!

1.eDP panel edid 3840x2160
2.eDP panel edid change -> 1920x1080
3.eDP panel edid change -> 3840x2160
4.change…But solid color screen was shown after alteration

The computer mouse was shown but ubuntu screen is covered by solid color.
Please let me know how i could solve these problems.
I think that the setting should be changed from framebuffer.

Could you share your solution?
So I can reproduce your new issue in my environment

Thanks!

1.eDP panel edid 3840x2160 pclk:533333000
2.eDP panel edid change -> 1920x1080 pclk:74250000
3.eDP panel edid change -> 3840x2160 pclk:533333000
4.The computer mouse was shown but ubuntu screen is covered by solid color.
solid color == computer wallpaper color

HDMI-0

DP-0

dmesg

[    9.516260] IPv6: ADDRCONF(NETDEV_UP): enx00044b664157: link is not ready
[    9.753989] gk20a gpu.0: GPCPLL initial settings: NA mode, M=1, N=34, P=3
[    9.904024] tegradc tegradc.0: blank - powerdown
[    9.905349] dp lt: state 5 (link training pass), hpd 1, pending_lt_evt 1
[    9.905352] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[    9.905355] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[    9.905357] dp lt: cur_hpd: 1, link cfg valid: 1, force disable: 1
[    9.923371] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[   10.451039] tegradc tegradc.0: unblank
[   10.776450] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[   10.804246] dp lt: state 4 (link training fail/disable), hpd 1, pending_lt_evt 1
[   10.804260] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[   10.804275] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   10.806962] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[   10.806978] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   10.807813] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[   10.807832] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[   10.807849] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[   10.807866] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[   10.811491] dp lt: CR not done
[   10.813351] dp lt: new config: lane 0: vs level: 0, pe level: 1, pc2 level: 0
[   10.813360] dp lt: new config: lane 1: vs level: 0, pe level: 1, pc2 level: 0
[   10.813367] dp lt: new config: lane 2: vs level: 0, pe level: 1, pc2 level: 0
[   10.813374] dp lt: new config: lane 3: vs level: 0, pe level: 1, pc2 level: 0
[   10.813380] dp lt: CR retry
[   10.813390] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[   10.813409] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   10.813427] dp lt: config: lane 0: vs level: 0, pe level: 1, pc2 level: 0
[   10.813444] dp lt: config: lane 1: vs level: 0, pe level: 1, pc2 level: 0
[   10.813460] dp lt: config: lane 2: vs level: 0, pe level: 1, pc2 level: 0
[   10.813476] dp lt: config: lane 3: vs level: 0, pe level: 1, pc2 level: 0
[   10.816184] dp lt: CR done
[   10.816201] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[   10.816222] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[   10.822879] dp lt: CE done
[   10.822900] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[   10.825450] tegradc tegradc.0: unblank
[   10.827465] tegradc tegradc.1: blank - powerdown
[   11.137575] IPv6: ADDRCONF(NETDEV_CHANGE): enx00044b664157: link becomes ready
[   11.160274] cgroup: systemd (1) created nested cgroup for controller "blkio" which has incomplete hierarchy support. Nested cgroups may change behavior in the future.
[   11.245567] tegradc tegradc.0: dp: irq event received
[   11.305956] tegradc tegradc.0: dp: link stable, ignore irq event
[   14.187498] tegradc tegradc.0: blank - powerdown
[   14.189278] dp lt: state 5 (link training pass), hpd 1, pending_lt_evt 1
[   14.189280] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[   14.189283] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   14.189285] dp lt: cur_hpd: 1, link cfg valid: 1, force disable: 1
[   14.207497] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[   14.727490] tegradc tegradc.0: unblank
[   15.052031] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[   15.064976] dp lt: state 4 (link training fail/disable), hpd 1, pending_lt_evt 1
[   15.064979] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[   15.064982] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   15.066328] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[   15.066335] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   15.066559] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[   15.066563] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[   15.066567] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[   15.066572] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[   15.067742] dp lt: CR not done
[   15.068603] dp lt: new config: lane 0: vs level: 0, pe level: 2, pc2 level: 0
[   15.068605] dp lt: new config: lane 1: vs level: 0, pe level: 2, pc2 level: 0
[   15.068606] dp lt: new config: lane 2: vs level: 0, pe level: 2, pc2 level: 0
[   15.068607] dp lt: new config: lane 3: vs level: 0, pe level: 2, pc2 level: 0
[   15.068608] dp lt: CR retry
[   15.068611] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[   15.068615] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   15.068620] dp lt: config: lane 0: vs level: 0, pe level: 2, pc2 level: 0
[   15.068624] dp lt: config: lane 1: vs level: 0, pe level: 2, pc2 level: 0
[   15.068629] dp lt: config: lane 2: vs level: 0, pe level: 2, pc2 level: 0
[   15.068633] dp lt: config: lane 3: vs level: 0, pe level: 2, pc2 level: 0
[   15.070063] dp lt: CR done
[   15.070066] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[   15.070070] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[   15.072477] dp lt: CE done
[   15.072480] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[   15.073026] tegradc tegradc.0: unblank
[   15.073036] tegradc tegradc.1: blank - powerdown
[   15.521178] tegradc tegradc.0: dp: irq event received
[   15.585961] tegradc tegradc.0: dp: link stable, ignore irq event
[   35.024879] tegradc tegradc.0: blank - powerdown
[   35.054253] dp lt: state 5 (link training pass), hpd 1, pending_lt_evt 1
[   35.054256] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[   35.054259] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   35.054261] dp lt: cur_hpd: 1, link cfg valid: 1, force disable: 1
[   35.072578] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[   37.645210] tegradc tegradc.0: dp: unplug event received
[   38.146911] tegradc tegradc.0: dp: plug event received
[   38.214434] tegradc tegradc.0: unblank
[   38.557439] tegradc tegradc.0: nominal-pclk:74250000 parent:74250000 div:1.0 pclk:74250000 73507500~80932500
[   38.592204] dp lt: state 4 (link training fail/disable), hpd 1, pending_lt_evt 1
[   38.592233] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[   38.592257] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   38.594046] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[   38.594085] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   38.594469] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[   38.594493] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[   38.594514] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[   38.594534] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[   38.597858] dp lt: CR not done
[   38.598782] dp lt: new config: lane 0: vs level: 0, pe level: 3, pc2 level: 0
[   38.598789] dp lt: new config: lane 1: vs level: 0, pe level: 3, pc2 level: 0
[   38.598794] dp lt: new config: lane 2: vs level: 0, pe level: 3, pc2 level: 0
[   38.598799] dp lt: new config: lane 3: vs level: 0, pe level: 3, pc2 level: 0
[   38.598804] dp lt: CR retry
[   38.598812] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[   38.598828] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   38.598846] dp lt: config: lane 0: vs level: 0, pe level: 3, pc2 level: 0
[   38.598860] dp lt: config: lane 1: vs level: 0, pe level: 3, pc2 level: 0
[   38.598874] dp lt: config: lane 2: vs level: 0, pe level: 3, pc2 level: 0
[   38.598887] dp lt: config: lane 3: vs level: 0, pe level: 3, pc2 level: 0
[   38.601352] dp lt: CR done
[   38.601361] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[   38.601372] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[   38.605334] dp lt: CE done
[   38.605344] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[   39.036685] tegradc tegradc.0: dp: irq event received
[   39.106424] tegradc tegradc.0: dp: link stable, ignore irq event
[   39.737521] tegradc tegradc.0: nominal-pclk:74250000 parent:74250000 div:1.0 pclk:74250000 73507500~80932500
[   39.744875] tegradc tegradc.0: blank - powerdown
[   39.748033] dp lt: state 5 (link training pass), hpd 1, pending_lt_evt 1
[   39.748038] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[   39.748042] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   39.748045] dp lt: cur_hpd: 1, link cfg valid: 1, force disable: 1
[   39.773807] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[   40.298696] tegradc tegradc.1: blank - powerdown
[   40.611179] tegradc tegradc.0: blank - powerdown
[   40.611417] tegradc tegradc.0: unblank
[   40.936371] tegradc tegradc.0: nominal-pclk:74250000 parent:74250000 div:1.0 pclk:74250000 73507500~80932500
[   40.938416] tegradc tegradc.0: dp: irq event received, ignoring
[   40.956789] dp lt: state 4 (link training fail/disable), hpd 1, pending_lt_evt 1
[   40.956810] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[   40.956832] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   40.959271] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[   40.959305] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   40.959686] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[   40.959708] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[   40.959729] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[   40.959749] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[   40.961853] dp lt: CR done
[   40.961876] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[   40.961903] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[   40.967351] dp lt: CE done
[   40.967371] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[   40.968690] tegradc tegradc.0: unblank
[   40.969062] tegradc tegradc.0: nominal-pclk:74250000 parent:74250000 div:1.0 pclk:74250000 73507500~80932500
[   40.969195] tegradc tegradc.1: blank - powerdown
[   43.752212] tegradc tegradc.0: blank - powerdown
[   43.801008] dp lt: state 5 (link training pass), hpd 1, pending_lt_evt 1
[   43.801012] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[   43.801015] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   43.801017] dp lt: cur_hpd: 1, link cfg valid: 1, force disable: 1
[   43.836269] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[   46.396440] tegradc tegradc.0: dp: unplug event received
[   46.896739] tegradc tegradc.0: dp: plug event received
[   46.987206] tegradc tegradc.0: unblank
[   47.318532] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[   47.342683] dp lt: state 4 (link training fail/disable), hpd 1, pending_lt_evt 1
[   47.342717] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[   47.342741] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   47.347136] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[   47.347174] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   47.347543] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[   47.347561] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[   47.347578] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[   47.347594] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[   47.349523] dp lt: CR done
[   47.349538] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[   47.349555] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[   47.353933] dp lt: CE done
[   47.353945] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[   47.723489] tegradc tegradc.0: dp: irq event received
[   47.786784] tegradc tegradc.0: dp: link stable, ignore irq event
[   48.467574] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[   48.562205] tegradc tegradc.0: blank - powerdown
[   48.566635] dp lt: state 5 (link training pass), hpd 1, pending_lt_evt 1
[   48.566638] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[   48.566640] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   48.566642] dp lt: cur_hpd: 1, link cfg valid: 1, force disable: 1
[   48.572829] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)
[   49.101965] tegradc tegradc.0: unblank
[   49.428718] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[   49.458539] dp lt: state 4 (link training fail/disable), hpd 1, pending_lt_evt 1
[   49.458555] dp lt: switching from state 4 (link training fail/disable) to state 0 (Reset)
[   49.458569] dp lt: state 0 (Reset), hpd 1, pending_lt_evt 0
[   49.460134] dp lt: switching from state 0 (Reset) to state 2 (clock recovery)
[   49.460149] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   49.460462] dp lt: config: lane 0: vs level: 0, pe level: 0, pc2 level: 0
[   49.460477] dp lt: config: lane 1: vs level: 0, pe level: 0, pc2 level: 0
[   49.460491] dp lt: config: lane 2: vs level: 0, pe level: 0, pc2 level: 0
[   49.460504] dp lt: config: lane 3: vs level: 0, pe level: 0, pc2 level: 0
[   49.462228] dp lt: CR not done
[   49.463345] dp lt: new config: lane 0: vs level: 0, pe level: 1, pc2 level: 0
[   49.463351] dp lt: new config: lane 1: vs level: 0, pe level: 1, pc2 level: 0
[   49.463357] dp lt: new config: lane 2: vs level: 0, pe level: 1, pc2 level: 0
[   49.463362] dp lt: new config: lane 3: vs level: 0, pe level: 1, pc2 level: 0
[   49.463368] dp lt: CR retry
[   49.463374] dp lt: switching from state 2 (clock recovery) to state 2 (clock recovery)
[   49.463386] dp lt: state 2 (clock recovery), hpd 1, pending_lt_evt 0
[   49.463401] dp lt: config: lane 0: vs level: 0, pe level: 1, pc2 level: 0
[   49.463415] dp lt: config: lane 1: vs level: 0, pe level: 1, pc2 level: 0
[   49.463429] dp lt: config: lane 2: vs level: 0, pe level: 1, pc2 level: 0
[   49.463443] dp lt: config: lane 3: vs level: 0, pe level: 1, pc2 level: 0
[   49.465853] dp lt: CR done
[   49.465862] dp lt: switching from state 2 (clock recovery) to state 3 (channel equalization)
[   49.465873] dp lt: state 3 (channel equalization), hpd 1, pending_lt_evt 0
[   49.470034] dp lt: CE done
[   49.470048] dp lt: switching from state 3 (channel equalization) to state 5 (link training pass)
[   49.472276] tegradc tegradc.0: unblank
[   49.472324] tegradc tegradc.1: blank - powerdown
[   49.473099] tegradc tegradc.0: nominal-pclk:533333000 parent:533332032 div:1.0 pclk:533332032 527999670~581332970
[   49.898384] tegradc tegradc.0: dp: irq event received
[   49.966059] tegradc tegradc.0: dp: link stable, ignore irq event


Hi CHIHONG,

I cannot see your image. Could you upload it to google drive and share it again?

post a picture on

Resolution has been changed by driver code revision.

I managed to fix the problem on my own.