Change the device tree for DisplayPort on DP1?

Will you see anything new printed from dmesg if you hotplug the DP cable?

No, nothing changes in the dmesg.log

Please go to /proc/device-tree and compare the sor and sor1 part.

Since your sor is still the old setting but just disabled, you can check if sor1 has anything missing.

okay, I will check everything again.

I have used sor as a template for sor1???

Yes, please use it as a template.

Hi,

for testing the → DP1_HPD → nvidia,hpd-gpio = <&gpio TEGRA_GPIO(CC, 1) 1>; /PN/
do I check with:

root@linux:/sys/kernel/debug
sudo -s
cat tegra_gpio

the tegra_gpio pins.

RESULT->
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL

→ plug out cable
CC: 7:0 92 80 80 00 00 10 101000

→ plug in cable
CC: 7:0 92 80 80 02 00 10 101000

The testing of hotplug with

root@linux/sys/kernel/debug/tegradc.0
cat hotplug

Always results in 0!

→ plug out cable
0

→ plug in cable
0

What is the reason???
What can I do?

maybe it is because of the file tegra210-porg-gpio-p3448-0000-b00.dtsi

#include <dt-bindings/gpio/tegra-gpio.h>

/ {
gpio: gpio@6000d000 {
gpio-init-names = “default”;
gpio-init-0 = <&gpio_default>;

	gpio_default: default {
		gpio-input = <
			TEGRA_GPIO(E, 6)
			TEGRA_GPIO(A, 5)
			TEGRA_GPIO(X, 4)
			TEGRA_GPIO(X, 5)
			TEGRA_GPIO(X, 6)
			TEGRA_GPIO(Y, 1)
			TEGRA_GPIO(Y, 2)
			TEGRA_GPIO(V, 0)
			TEGRA_GPIO(V, 1)
			TEGRA_GPIO(Z, 2)
			TEGRA_GPIO(G, 2)
			TEGRA_GPIO(G, 3)
			TEGRA_GPIO(H, 2)
			TEGRA_GPIO(H, 5)
			TEGRA_GPIO(H, 6)
			TEGRA_GPIO(I, 1)
			TEGRA_GPIO(I, 2)
			TEGRA_GPIO(CC, 4)
			>;
		gpio-output-low = <
			TEGRA_GPIO(Z, 3)
			TEGRA_GPIO(H, 0)
			TEGRA_GPIO(H, 3)
			TEGRA_GPIO(H, 4)
			TEGRA_GPIO(H, 7)
			TEGRA_GPIO(I, 0)
			>;
		gpio-output-high = <
			TEGRA_GPIO(BB, 0)
			TEGRA_GPIO(A, 6)
			TEGRA_GPIO(X, 3)
			TEGRA_GPIO(Z, 0)
			TEGRA_GPIO(CC, 7)
			>;
	};
};

};

And what I still ask myself, is 0x5b 0xe1 0x01 really → TEGRA_GPIO(CC, 1) ???

nvidia,hpd-gpio = <0x5b 0xe1 0x01>;

Sorry, looks like nvidia,hpd-gpio is still needed for dp case.

→ plug out cable
CC: 7:0 92 80 80 00 00 10 101000
→ plug in cable
CC: 7:0 92 80 80 02 00 10 101000

It looks like the pin has response to your input.

Are you sure the dpaux1 also has same configuration as dpaux?

Hello,
this is how sor/dpaux and sor1/dpaux1 looks in the current device tree:

	sor {
		compatible = "nvidia,tegra210-sor";
		reg = <0x0 0x54540000 0x0 0x40000>;
		reg-names = "sor";
		status = "disabled";
		nvidia,sor-ctrlnum = <0x0>;
		nvidia,dpaux = <0x73>;
		nvidia,xbar-ctrl = <0x2 0x1 0x0 0x3 0x4>;
		clocks = <0x26 0xde 0x26 0xb6 0x26 0x12f>;
		clock-names = "sor_safe", "sor0", "pll_dp";
		resets = <0x26 0xb6>;
		reset-names = "sor0";
		nvidia,sor-audio-not-supported;
		linux,phandle = <0x6d>;
		phandle = <0x6d>;

		hdmi-display {
			compatible = "hdmi,display";
			status = "disabled";
			linux,phandle = <0x116>;
			phandle = <0x116>;
		};

		dp-display {
			compatible = "dp, display";
			status = "disabled";
			linux,phandle = <0x117>;
			phandle = <0x117>;
		};

		prod-settings {
			#prod-cells = <0x3>;

			prod_c_dp {
				prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
			};
		};
	};

	sor1 {
		compatible = "nvidia,tegra210-sor1";
		reg = <0x0 0x54580000 0x0 0x40000>;
		reg-names = "sor";
		interrupts = <0x0 0x4c 0x4>;
		status = "okay";
		nvidia,sor-ctrlnum = <0x1>;
		nvidia,dpaux = <0x74>;
		nvidia,xbar-ctrl = <0x0 0x1 0x2 0x3 0x4>;
		clocks = <0x26 0x16f 0x26 0xde 0x26 0x16e 0x26 0xb7 0x26 0x12f 0x26 0xf3 0x26 0xca 0x26 0x7d 0x26 0x6f 0x26 0x80>;
		clock-names = "sor1_ref", "sor_safe", "sor1_pad_clkout", "sor1", "pll_dp", "pll_p", "maud", "hda", "hda2codec_2x", "hda2hdmi";
		resets = <0x26 0xb7 0x26 0x7d 0x26 0x6f 0x26 0x80>;
		reset-names = "sor1", "hda_rst", "hda2codec_2x_rst", "hda2hdmi_rst";
		nvidia,sor1-output-type = "dp";
		nvidia,active-panel = <0x75>;
		linux,phandle = <0x6a>;
		phandle = <0x6a>;

		hdmi-display {
			compatible = "hdmi,display";
			status = "disabled";
			linux,phandle = <0x118>;
			phandle = <0x118>;

			disp-default-out {
				nvidia,out-xres = <0x1000>;
				nvidia,out-yres = <0x870>;
			};
		};

		dp-display {
			compatible = "dp, display";
			status = "okay";
			nvidia,hpd-gpio = <0x5b 0xe1 0x1>;
			nvidia,is_ext_dp_panel = <0x1>;
			linux,phandle = <0x75>;
			phandle = <0x75>;

			disp-default-out {
				nvidia,out-type = <0x3>;
				nvidia,out-align = <0x0>;
				nvidia,out-order = <0x0>;
				nvidia,out-flags = <0x0>;
				nvidia,out-pins = <0x1 0x0 0x2 0x0 0x3 0x0 0x0 0x1>;
				nvidia,out-parent-clk = "pll_d2";
			};

			dp-lt-settings {

				lt-setting@0 {
					nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
					nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
					nvidia,tx-pu = <0x0>;
					nvidia,load-adj = <0x3>;
				};

				lt-setting@1 {
					nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					nvidia,lane-preemphasis = <0x0 0x0 0x0 0x0>;
					nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
					nvidia,tx-pu = <0x0>;
					nvidia,load-adj = <0x4>;
				};

				lt-setting@2 {
					nvidia,drive-current = <0x0 0x0 0x0 0x0>;
					nvidia,lane-preemphasis = <0x1 0x1 0x1 0x1>;
					nvidia,post-cursor = <0x0 0x0 0x0 0x0>;
					nvidia,tx-pu = <0x0>;
					nvidia,load-adj = <0x6>;
				};
			};
		};

		prod-settings {
			#prod-cells = <0x3>;

			prod_c_dp {
				prod = <0x5c 0xf000f10 0x1000310 0x60 0x3f00100 0x400100 0x68 0x2000 0x2000 0x70 0xffffffff 0x0 0x180 0x1 0x1>;
			};
		};
	};

	dpaux {
		compatible = "nvidia,tegra210-dpaux";
		reg = <0x0 0x545c0000 0x0 0x40000>;
		interrupts = <0x0 0x9f 0x4>;
		nvidia,dpaux-ctrlnum = <0x0>;
		status = "okay";
		clocks = <0x26 0xb5>;
		clock-names = "dpaux";
		resets = <0x26 0xb5>;
		reset-names = "dpaux";
		linux,phandle = <0x73>;
		phandle = <0x73>;

		prod-settings {
			#prod-cells = <0x3>;

			prod_c_dpaux_dp {
				prod = <0x124 0x37fe 0x24c2>;
			};

			prod_c_dpaux_hdmi {
				prod = <0x124 0x700 0x400>;
			};
		};
	};

	dpaux1 {
		compatible = "nvidia,tegra210-dpaux1";
		reg = <0x0 0x54040000 0x0 0x40000>;
		interrupts = <0x0 0xb 0x4>;
		nvidia,dpaux-ctrlnum = <0x1>;
		status = "okay";
		clocks = <0x26 0xcf>;
		clock-names = "dpaux1";
		resets = <0x26 0xcf>;
		reset-names = "dpaux1";
		linux,phandle = <0x74>;
		phandle = <0x74>;

		prod-settings {
			#prod-cells = <0x3>;

			prod_c_dpaux_dp {
				prod = <0x124 0x37fe 0x24c2>;
			};

			prod_c_dpaux_hdmi {
				prod = <0x124 0x700 0x400>;
			};
		};
	};

Could you also check the power tree “hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-fixed-p3448-0000-a00.dtsi” and see if it matches your desgin?

On nano devkit, when we plug the DP cable to device, I can see the avdd-io-edp-1v05 is pulled to high.

gpio-511 ( |avdd-io-edp-1v05 ) out hi

Since the case on your side is the HPD has 1v8 but driver gives no response, it seems the power source is incorrect.

That is exactly it !

True, with me it is always:

gpio-511 ( |avdd-io-edp-1v05 ) out lo !!!

Although the signal arrives:

Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL

→ plug out cable
CC: 7:0 92 80 80 00 00 10 101000

→ plug in cable
CC: 7:0 92 80 80 02 00 10 101000

What exactly should i check in the file tegra210-porg-fixed-p3448-0000-a00.dtsi ???

The file currently looks like this:

tegra210-porg-fixed-p3448-0000-a00.dtsi (3.9 KB)

hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-power-tree-p3448-0000-a00.dtsi

This file defines the power source of DP and HDMI.

And those “p3448_avdd_io_edp” regulators are defined in tegra210-porg-fixed-p3448-0000-a00.dtsi. You have to check if the power source is really that one with your board design. For example, currently, p3448_avdd_io_edp is provided by gpio = <&max77620 7 0>. Is your DP power also uses the gpio from our PMIC as source?

It is connected exactly like this:

DP1_HPD = 96

image

Hi @ElectronicSystems ,

  1. Could you measure if the PWR on your connector really has 3.3v?

  2. You are using tegradc.0 now but all the power regulator is under tegradc.1 DT, are you sure you really move this to tegradc.0 too? Besides sor, please also compare the tegradc.0 and tegradc.1 on /proc/device-tree.

I have measured 3.3V at PWR-Pin
but why is that important?

No, I have to take a closer look at that again.

If you have nano devkit, you can plug in a dp cable and see the dmesg. It shall printed something like below.

tegradc tegradc.1: dp: plug event received

However, this does not happen on your side. Such log is printed by driver “kernel/nvidia/drivers/video/tegra/dc/dp.c” and it is done by dpaux.

You can use dtc tool to convert the whole dtb file back to dts and compare your dts with official dts. Generally there are just sor/tegradc/ pinmux and dpaux to compare. If all of them are matched, then I have no idea from software part.

Hi,

exactly, I had not exchanged it!

Now I get with dmesg:

[ 33.909503] avdd-io-edp-1v05: disabling

I think I still need to adjust gpio = <&max77620 7 0>?
I want to query pin 96 ?