Changing sensor driver from 10 bit to 12 bit failed with NvArgusCameraSrc - v4l2-ctl works

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
1

Hello,
I added to my custom sensor driver mode table and to my device tree a new mode, which is 12 bit instead of my other modes, which are 10 bit.

V4l2-ctl works fine with it, but nvarguscamerasrc does not.

I looked up how to change device tree for 12 bit in imx185 driver and accordingly only changed these parameters:

dynamic_pixel_bit_depth = "12";
csi_pixel_bit_depth = "12";

Is there anything else which need to be changed for ISP to work with 12bit?
What about line_length paramter. Can a bad value result in failing ISP while v4l2-ctl is working?
Does ISP work with sensor device tree with mixed 10bit / 12bit modes?

this is my related dmesg output:

[  +1.502275] fence timeout on [ffffffc1b7437900] after 1500ms
[  +0.000029] tegra194-vi5 15c10000.vi: no reply from camera processor
[  +0.000024] tegra194-vi5 15c10000.vi: vi capture get status failed
[  +0.000458] name=[nvhost_sync:32], current value=0 waiting value=1
[  +0.000029] ---- mlocks ----

[  +0.000073] ---- syncpts ----
[  +0.000112] id 23 (gv11b_510_user) min 29 max 0 refs 1 (previous client : )
[  +0.000027] id 35 (gv11b_506) min 3 max 3 refs 1 (previous client : )
[  +0.000009] id 36 (gv11b_505) min 4 max 4 refs 1 (previous client : )
[  +0.000008] id 37 (gv11b_504) min 3 max 3 refs 1 (previous client : )
[  +0.000008] id 38 (gv11b_503) min 3 max 3 refs 1 (previous client : )
[  +0.000008] id 39 (gv11b_502) min 3 max 3 refs 1 (previous client : )

[  +0.001023] ---- channels ----
[  +0.000070]
              channel 2 - 15820000.se

[  +0.000006] NvHost basic channel registers:
[  +0.000012] CMDFIFO_STAT_0:  00002040
[  +0.000007] CMDFIFO_RDATA_0: d14002c0
[  +0.000013] CMDP_OFFSET_0:   00000000
[  +0.000007] CMDP_CLASS_0:    00000000
[  +0.000006] CHANNELSTAT_0:   00000000
[  +0.000007] The CDMA sync queue is empty.

[  +0.000013]
              channel 3 - 15830000.se

[  +0.000005] NvHost basic channel registers:
[  +0.000006] CMDFIFO_STAT_0:  00002040
[  +0.000007] CMDFIFO_RDATA_0: a6cd80a0
[  +0.000008] CMDP_OFFSET_0:   00000000
[  +0.000006] CMDP_CLASS_0:    00000000
[  +0.000006] CHANNELSTAT_0:   00000000
[  +0.000006] The CDMA sync queue is empty.

[  +0.000013]
              channel 4 - 15840000.se

[  +0.000004] NvHost basic channel registers:
[  +0.000006] CMDFIFO_STAT_0:  00002040
[  +0.000006] CMDFIFO_RDATA_0: 42200010
[  +0.000007] CMDP_OFFSET_0:   00000000
[  +0.000006] CMDP_CLASS_0:    00000000
[  +0.000008] CHANNELSTAT_0:   00000000
[  +0.000006] The CDMA sync queue is empty.

[  +0.000019]
              ---- host general irq ----

[  +0.000008] sync_intc0mask = 0x00000001
[  +0.000007] sync_intmask = 0x50000003
[  +0.000005]
              ---- host syncpt irq mask ----

[  +0.000004]
              ---- host syncpt irq status ----

[  +0.000010] syncpt_thresh_cpu0_int_status(0) = 0x00000000
[  +0.000009] syncpt_thresh_cpu0_int_status(1) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(2) = 0x00000000
[  +0.000008] syncpt_thresh_cpu0_int_status(3) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(4) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(5) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(6) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(7) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(8) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(9) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(10) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(11) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(12) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(13) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(14) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(15) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(16) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(17) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(18) = 0x00000000
[  +0.000007] syncpt_thresh_cpu0_int_status(19) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(20) = 0x00000000
[  +0.000006] syncpt_thresh_cpu0_int_status(21) = 0x00000000

Thank you for all the help!

3

Nvargus able support mixed 10bit / 12bit modes.
Try to make remove all sensor mode report 12bit mode only and make the those control function like exposure/frame rate control as dummy function to try.

4

I tried the dummy functions for exposure und framerate.
Didn’t help. Will try to remove other sensor modes.

5

I get this error when switchting to only mode with 12 bit.

You can see it fails in camera_common_g_fmt. Does this mean it fails because of the 12 bit?

[    5.253979] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[    5.254174] Mem abort info:
[    5.254234]   ESR = 0x96000005
[    5.254302]   Exception class = DABT (current EL), IL = 32 bits
[    5.254409]   SET = 0, FnV = 0
[    5.254474]   EA = 0, S1PTW = 0
[    5.254541] Data abort info:
[    5.254605]   ISV = 0, ISS = 0x00000005
[    5.254678]   CM = 0, WnR = 0
[    5.254741] user pgtable: 4k pages, 39-bit VAs, pgd = ffffffc1ea111000
[    5.254940] [0000000000000000] *pgd=0000000000000000, *pud=0000000000000000
[    5.255091] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[    5.255196] Modules linked in: OS08A20(+) nvgpu ip_tables x_tables
[    5.255374] CPU: 0 PID: 4410 Comm: systemd-udevd Not tainted 4.9.253-tegra #27
[    5.255507] Hardware name: NVIDIA Jetson Xavier NX Developer Kit (DT)
[    5.255797] task: ffffffc1eaef7000 task.stack: ffffffc1e5e38000
[    5.256258] PC is at camera_common_g_fmt+0x44/0xc8
[    5.256624] LR is at camera_common_g_fmt+0x30/0xc8
[    5.256998] pc : [<ffffff8008b472b4>] lr : [<ffffff8008b472a0>] pstate: 40400045
[    5.262005] sp : ffffffc1e5e3b6a0
[    5.265074] x29: ffffffc1e5e3b6a0 x28: 000000000000300d
[    5.270695] x27: ffffffc1f4d8cc20 x26: 0000000000000002
[    5.276527] x25: 0000000000000038 x24: 0000000000000001
[    5.281880] x23: ffffffc1ee4ee450 x22: ffffffc1ee4ee450
[    5.287725] x21: ffffffc1ee4ee418 x20: 0000000000000000
[    5.293152] x19: ffffffc1e5e3b770 x18: 0000000000000001
[    5.298837] x17: 000000000299a0b3 x16: 0000000000000001
[    5.304527] x15: ffffffffffffffff
[    5.306001] random: crng init done
[    5.306005] random: 7 urandom warning(s) missed due to ratelimiting
[    5.317397] x14: ffffffc1e5e3b6a0
[    5.320653] x13: ffffffc1e5e3b5a5 x12: ffffffffffffffff
[    5.326400] x11: ffffffc1e5e3b560 x10: ffffffc1e5e3b560
[    5.331907] x9 : 0000000000000002 x8 : 0000000000000002
[    5.337000] x7 : ffffff8008fd71c0 x6 : 0000000000000090
[    5.342588] x5 : 000000000000008d x4 : 0000000000000001
[    5.347923] x3 : 0000000000010000 x2 : 0000000000000000
[    5.353012] x1 : ffffffc1eaef7000 x0 : 0000000000000001

[    5.360179] Process systemd-udevd (pid: 4410, stack limit = 0xffffffc1e5e38000)
[    5.366654] Call trace:
[    5.369023] [<ffffff8008b472b4>] camera_common_g_fmt+0x44/0xc8
[    5.374885] [<ffffff8008b4d458>] v4l2sd_get_fmt+0x28/0x38
[    5.380398] [<ffffff8008b355f4>] tegra_channel_fmts_bitmap_init+0x13c/0x268
[    5.387482] [<ffffff8008b36e0c>] tegra_channel_init_subdevices+0x17c/0x798
[    5.393967] [<ffffff8008b38050>] tegra_vi_graph_notify_complete+0x2e8/0x6e8
[    5.400356] [<ffffff8008b1b714>] v4l2_async_test_notify+0x104/0x120
[    5.406463] [<ffffff8008b1b950>] v4l2_async_register_subdev+0x88/0x100
[    5.412590] [<ffffff8008b4d278>] tegracam_v4l2subdev_register+0xf0/0x190
[    5.418723] [<ffffff80011c94a8>] OS08A20_probe+0x260/0x3c0 [OS08A20]
[    5.425016] [<ffffff8008ae488c>] i2c_device_probe+0x144/0x258
[    5.430791] [<ffffff80087803c0>] driver_probe_device+0x298/0x448
[    5.436392] [<ffffff800878064c>] __driver_attach+0xdc/0x128
[    5.441993] [<ffffff800877dc7c>] bus_for_each_dev+0x5c/0xa8
[    5.447680] [<ffffff800877fa00>] driver_attach+0x30/0x40
[    5.453366] [<ffffff800877f434>] bus_add_driver+0x20c/0x2a8
[    5.458964] [<ffffff8008781584>] driver_register+0x6c/0x110
[    5.464485] [<ffffff8008ae4f7c>] i2c_register_driver+0x4c/0xb0
[    5.470697] [<ffffff80011d0018>] OS08A20_i2c_driver_init+0x18/0x30 [OS08A20]
[    5.477525] [<ffffff8008083b3c>] do_one_initcall+0x44/0x130
[    5.483558] [<ffffff8008f5fcec>] do_init_module+0x64/0x1b0
[    5.488719] [<ffffff80081569bc>] load_module+0x10ac/0x12e0
[    5.494055] [<ffffff8008156ea0>] SyS_finit_module+0xd8/0xf0
[    5.500092] [<ffffff800808395c>] __sys_trace_return+0x0/0x4
[    5.505869] ---[ end trace 0372f49e7c0f1433 ]---
6

I don’t think so.
Have a reference to imx185 for the 10/12bit mixed driver.

7

Is pixel depth set in the driver also or only in device tree?

8

The error disappeared when changing from bggr bayer pattern in device tree to rggb bayer pattern (like the imx185). Is it possible you dont have support for 12 bit bggr in your code? Can I add it somewhere?

9

Now everything is working except that ISP thinks I have rggb bayer pattern, which is wrong for my sensor.

10

Adding this:

 {
        MEDIA_BUS_FMT_SBGGR12_1X12,
        V4L2_COLORSPACE_SRGB,
        V4L2_PIX_FMT_SBGGR12,
    },

to this struct:

static const struct camera_common_colorfmt camera_common_color_fmts[] = {

in

kernel/nvidia/drivers/media/platform/tegra/camera/camera_common.c

fixed the issue. Thanks!

1 Like
12

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