Changing UARTC parent clock frequency

I am using UARTC (the debug UART) for communications with a microcontroller from the Xavier NX. I have disabled its functionality as a debug serial port in JetPack 4.6 so I can use it for my own purposes. However, I want to use as fast a baud rate as possible. Even though both the micro and the Xavier are capable of fast baud rates, their differing base clocks prevent me from matching baud rates past about 2 Mbaud. I would like to reprogram the parent clock on UARTC to match a multiple of the parent clock of the microcontroller so that I can match baud rates exactly and get up to 9 Mbaud (which requires a parent clock of at least 144 MHz). I have switched the UARTC parent clock from TEGRA194_CLK_PLLP_OUT0 to TEGRA194_CLK_PLLC4_MUXED to faciltate this (since TEGRA194_CLK_PLLP_OUT0 is used by tons of peripherals but TEGRA194_CLK_PLLC4_MUXED is only used by SDHCI it seems). The PLLC4_MUXED clock appears to be muxed from the PLLC4_VCO_DIV2 clock so it looks like I would want to reprogram this clock to a value close to its original value, but a multiple of my microcontroller clock.

However, I am struggling to figure out how I can reprogram this clock frequency. I also am not entirely sure of the impact that doing so will have (although I realize it may affect the SDHCI interface and its rates). Is it safe for me to do this, and if so, how do I go about it?

Any help would be appreciated.

hello dan.madill,

had you update device tree to change the clock sources?

        uartc: serial@c280000 {
                compatible = "nvidia,tegra186-hsuart";
                clocks = <&bpmp_clks TEGRA194_CLK_UARTC>,
                        <&bpmp_clks TEGRA194_CLK_PLLP_OUT0>;

you may also try update the clock partners as below.
please check # cat /sys/kernel/debug/clk/uartc/clk_possible_parents for all available clocks.
and…
please configure a new sources to update the settings. # echo new_source > /sys/kernel/debug/clk/uartc/clk_parent

Hello Jerry,

I already updated the device tree to use TEGRA194_CLK_PLLC4_MUXED instead of TEGRA194_CLK_PLLP_OUT0. I looked at all the other parent clocks and the only one that seemed to make sense was the TEGRA194_CLK_PLLC4_MUXED clock because it does not appear to be used by much in the NX and to get 9 MBaud I will have to reprogram its rate. By switching to the MUXED clock I was already able to get up to 3 MBaud just because the MUXED clock frequency was better matched to get that baud rate, but I would like to reprogram its rate to get up to the full 9 MBaud. I thought I already explained that in my post, but I guess it wasn’t clear.

hello dan.madill,

Linux kernel has restriction on speed, maximum speed macro (B4000000) present is 4Mbps.
you may see-also this topic, Jetson TX2 UART clock - #10 by linuxdev

Hello Jerry,

Linux supports custom baud rates as well so baud rates are not restricted to the standard rates provided by the macros. On our last design with a TX2 we communicated at 12.5 Mbaud using the UART. I do not recall having to modify the Linux kernel to achieve this rate but it’s possible I did. I could always modify the serial driver for the Xavier.

Hello Jerry,

So is there a way to reprogram the PLLC4_VCO_DIV2 clock to be a different rate?

hello dan.madill,

please refer to Xavier TRM for [10.4.2.23 UART Boot] session.

Thank you, Jerry. I had missed that section so I will work my way through that.