Check pinmux on spi0&1 on jetson-nano

Hi, Shane
I am using r32.3.1.
The BSP files are Tegra210_Linux_R32.3.1_aarch64.tbz2, Tegra_Linux_Sample-Root-Filesystem_R32.3.1_aarch64.tbz2, public_sources.tbz2.

I am using an jetson-nano board with emmc flash. The jetson-io.py doesn’t work on my board.

The GPIO looks like no correct.
Have a check below.

Hi, Shane
Thanks a lot. But it only enable spidev0.0, and only configure 4 pins, I need enable four spidev. They spidev0.0, spidev0.1, spidev1.0, spidev1.1.
So there are 10 pins to be configured. Could you guide me how to modify u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
and kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi

Could you check if you can run below command

sudo find /opt/nvidia/jetson-io/ -mindepth 1 -maxdepth 1 -type d -exec touch {}/ init .py ;
sudo /opt/nvidia/jetson-io/jetson-io.py

https://docs.nvidia.com/jetson/l4t/index.html#page/Tegra%20Linux%20Driver%20Package%20Development%20Guide%2Fhw_setup_jetson_io.html

Yes. I had tried this. But it doesn’t help. And I also see jetson-io.py doesn’t support emmc flash on another ticket.

OK, I see.
Then you may need to build the u-boot and follow below patch remove the GPIO(B, x x) these group for the SPI1

I see all the pin are configured as IN . Should we use OUT0 or OUT1 for SPI CLK,MOSI,CSx pins?

Just comment them out, don’t need to configure it no matter as IN or OUT.
And you should be able see the different with the cat /sys/kernel/debug/tegra_gpio

Hi, Shane
I had done below modifications. But I don’t see too much difference in tegra_gpio

Modifications:
cd /home/jetson/Linux_for_Tegra/source/public
vi u-boot/board/nvidia/p3450-porg/pinmux-config-p3450-porg.h
static const struct tegra_gpio_config p3450_porg_gpio_inits = {
GPIO_INIT(B, 4, IN),
GPIO_INIT(B, 5, IN),
GPIO_INIT(B, 6, IN),
GPIO_INIT(B, 7, IN),
GPIO_INIT(DD, 0, IN),
GPIO_INIT(C, 0, IN),
GPIO_INIT(C, 1, IN),
GPIO_INIT(C, 2, IN),
GPIO_INIT(C, 3, IN),
GPIO_INIT(C, 4, IN),

Model: P3448 180-l3448-DAAA-B01
root@yisp-desktop:~# cat /proc/device-tree/nvidia,dtsfilename
/dvs/git/dirty/git-master_linux/kernel/kernel-4.9/arch/arm64/boot/dts/…/…/…/…/…/…/hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0002-p3449-0000-b00.dts

head -n 30 ./hardware/nvidia/platform/t210/porg/kernel-dts/tegra210-p3448-0002-p3449-0000-b00.dts
#include “tegra210-porg-p3448-common.dtsi”
#include “porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi”
#include “porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi”

vi ./hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi
gpio-input = <
TEGRA_GPIO(B, 4)
TEGRA_GPIO(B, 5)
TEGRA_GPIO(B, 6)
TEGRA_GPIO(B, 7)
TEGRA_GPIO(DD, 0)
TEGRA_GPIO(C, 0)
TEGRA_GPIO(C, 1)
TEGRA_GPIO(C, 2)
TEGRA_GPIO(C, 3)
TEGRA_GPIO(C, 4)

vi ./hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-pinmux-p3448-0002-b00.dtsi
spi2_mosi_pb4 {
nvidia,pins = “spi2_mosi_pb4”;
- nvidia,function = “rsvd2”;
+ nvidia,function = “spi2”;
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
spi2_miso_pb5 {
- nvidia,pins = “spi2_miso_pb5”;
+ nvidia,function = “spi2”;
spi2_sck_pb6 {
- nvidia,pins = “spi2_sck_pb6”;
+ nvidia,function = “spi2”;
spi2_cs0_pb7 {
- nvidia,pins = “spi2_cs0_pb7”;
+ nvidia,function = “spi2”;
spi2_cs1_pdd0 {
- nvidia,pins = “spi2_cs1_pdd0”;
+ nvidia,function = “spi2”;
spi1_mosi_pc0 {
- nvidia,pins = “spi1_mosi_pc0”;
+ nvidia,function = “spi1”;
spi1_miso_pc1 {
nvidia,pins = “spi1_miso_pc1”;
- nvidia,function = “rsvd1”;
+ nvidia,function = “spi1”;
spi1_sck_pc2 {
nvidia,pins = “spi1_sck_pc2”;
- nvidia,function = “rsvd1”;
+ nvidia,function = “spi1”;
spi1_cs0_pc3 {
nvidia,pins = “spi1_cs0_pc3”;
- nvidia,function = “rsvd1”;
+ nvidia,function = “spi1”;
spi1_cs1_pc4 {
nvidia,pins = “spi1_cs1_pc4”;
- nvidia,function = “rsvd1”;
+ nvidia,function = “spi1”;

How do you flash the u-boot? Have a try the binary from the github to make sure your modification.

Hi, Shane
After do the above modification. I rebuild uboot and kernel. Then use flash.sh to program the board. The steps like below.

2.rebuild
cd /home/jetson/Linux_for_Tegra/source/public/
cd u-boot
export CROSS_COMPILE=/home/jetson/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
make distclean
make p3450-porg_defconfig
make
cp u-boot.bin …/…/…/bootloader/t210ref/p3450-porg/

cd /home/jetson/Linux_for_Tegra
cd source/public/
cd kernel/kernel-4.9/
export TEGRA_KERNEL_OUT=/home/jetson/kernel_out
export CROSS_COMPILE=/home/jetson/gcc-linaro-7.3.1-2018.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
export LOCALVERSION=-tegra
make ARCH=arm64 O=$TEGRA_KERNEL_OUT
cp /home/jetson/kernel_out/arch/arm64/boot/Image /home/jetson/Linux_for_Tegra/kernel/Image
cp /home/jetson/kernel_out/arch/arm64/boot/dts/tegra210-p3448-*.dtb /home/jetson/Linux_for_Tegra/kernel/dtb/

3.Then program the board.
cd /home/jetson/Linux_for_Tegra/
./flash.sh jetson-nano-emmc mmcblk0p1

replace bootloader/t210ref/p3450-porg/u-boot.bin with the u-boot-spidev0-0.bin from github.
I see below info:
root@yisp-desktop:/home/yisp# cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
A: 0:0 64 40 40 04 00 00 000000
B: 0:1 f0 00 00 00 00 00 000000
C: 0:2 1f 00 00 00 00 00 000000
D: 0:3 00 00 00 00 00 00 000000
E: 1:0 40 00 00 40 00 00 000000
F: 1:1 00 00 00 00 00 00 000000
G: 1:2 0c 00 00 00 00 00 000000
H: 1:3 fd 99 00 60 00 00 000000
I: 2:0 07 07 03 00 00 00 000000
J: 2:1 f0 00 00 00 00 00 000000
K: 2:2 00 00 00 00 00 00 000000
L: 2:3 00 00 00 00 00 00 000000
M: 3:0 00 00 00 00 00 00 000000
N: 3:1 00 00 00 00 00 00 000000
O: 3:2 00 00 00 00 00 00 000000
P: 3:3 00 00 00 00 00 00 000000
Q: 4:0 00 00 00 00 00 00 000000
R: 4:1 00 00 00 00 00 00 000000
S: 4:2 a0 80 00 00 00 00 000000
T: 4:3 01 01 00 00 00 00 000000
U: 5:0 00 00 00 00 00 00 000000
V: 5:1 03 00 00 03 00 00 000000
W: 5:2 00 00 00 00 00 00 000000
X: 5:3 78 08 08 30 00 60 606000
Y: 6:0 06 00 00 06 00 00 000000
Z: 6:1 0f 08 00 07 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 01 00 00 000000
CC: 7:0 92 80 80 00 00 12 121200
DD: 7:1 01 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000
root@yisp-desktop:/home/yisp#

Did you remove all of the gpio group B and C from this file …/hardware/nvidia/platform/t210/porg/kernel-dts/porg-platforms/tegra210-porg-gpio-p3448-0002-b00.dtsi ?

Just check r32.3.1 u-boot already remove the GPIO init code you should be able use original u-boot.bin and remove the GPIO define in the dtsi file that should be working.

Hi, Shane
Thanks for helps. Could you help check whether the below configs are right.

root@yisp-desktop:/home/yisp# cat /sys/kernel/debug/tegra_gpio
Name:Bank:Port CNF OE OUT IN INT_STA INT_ENB INT_LVL
A: 0:0 64 40 40 04 00 00 000000
B: 0:1 00 00 00 00 00 00 000000
C: 0:2 00 00 00 00 00 00 000000
D: 0:3 00 00 00 00 00 00 000000
E: 1:0 40 00 00 40 00 00 000000
F: 1:1 00 00 00 00 00 00 000000
G: 1:2 0c 00 00 00 00 00 000000
H: 1:3 fd 99 00 60 00 00 000000
I: 2:0 07 07 03 00 00 00 000000
J: 2:1 f0 00 00 00 00 00 000000
K: 2:2 00 00 00 00 00 00 000000
L: 2:3 00 00 00 00 00 00 000000
M: 3:0 00 00 00 00 00 00 000000
N: 3:1 00 00 00 00 00 00 000000
O: 3:2 00 00 00 00 00 00 000000
P: 3:3 00 00 00 00 00 00 000000
Q: 4:0 00 00 00 00 00 00 000000
R: 4:1 00 00 00 00 00 00 000000
S: 4:2 a0 80 00 00 00 00 000000
T: 4:3 01 01 00 00 00 00 000000
U: 5:0 00 00 00 00 00 00 000000
V: 5:1 03 00 00 03 00 00 000000
W: 5:2 00 00 00 00 00 00 000000
X: 5:3 78 08 08 70 00 60 606000
Y: 6:0 06 00 00 06 00 00 000000
Z: 6:1 0f 08 00 05 00 04 000400
AA: 6:2 00 00 00 00 00 00 000000
BB: 6:3 01 00 00 01 00 00 000000
CC: 7:0 92 80 80 00 00 12 121200
DD: 7:1 00 00 00 00 00 00 000000
EE: 7:2 00 00 00 00 00 00 000000
FF: 7:3 00 00 00 00 00 00 000000

Now the enable bits of GPIO B and C group are clean. That’s correct now.
Could you attached the dtb here for some others reference.

Hi, Shane
Thanks a lot. The SPI interfaces are working now.
The system doesn’t allow upload dtb file. So I change the file extension to dtb.loggz.
tegra210-p3448-0002-p3449-0000-b00.dtb.loggz (209.5 KB)

Thanks ysp123ysp
I attached the u-boot.bin here for someone need to enable SPI function. Rename it to u-boot.bin and replace the …/Linux_for_tegra/bootloader/t210ref/p3450-porg/u-boot.bin and reflash the device.

u-boot.bin.txt (469.8 KB)

Hi, Shane
The above modifications are based on Sample-Root-Filesystem_R32.3.1, Tegra210_Linux_R32.3.1 and L4T R32.3.1 BSP source code. But I finally find that the end customer’s application was based on R32.2.1.
So Could you please kindly help check which option in below will be ok? Thanks a lot.
Merging modification from R32.3.1 to R32.2.1:
1#, Only replace the Sample rootfs with R32.2.1, the others are from R32.3.1
2# use L4T sample rootfs and Linux driver package are from R32.2.1, And add my customized uboot.bin, DTB file and kernel Image which are based on L4T BSP soucecode R32.3.2
3# use the L4T sample rootfs, Linux driver package, L4T BSP source code are from R32.2.1. Then apply the modifications to sourcecode. Then rebuild the binaries and program the board.

The 2 and 3 both should be OK.