Clarification on power rail for AVDD_HDMI

Hi,
what is the function of the mosfet Q9A2 at page 9 in the schematic of the Jetson TK1 board?
At first glance, I was thinking it was supposed to gate the power rail +3.3V_RUN, enabled via the +1.05V_RUN rail.
Anyway, since the source is directed toward the gated power rail, current would flow through the inverse diode even if disabled.
Is there anything I am missing?

Thank you.

Hi Roberto,

On the top of it you can read “P-MOSFET TO PREVENT BACKDRIVE ON AVDD_HDMI” so it’s only to prevent return current path.
Another thing you can observe is that there is “R2A10” with EN_VDD_HDMI in parallel of “R2A9” with 1.05_RUN is not populated
That way it is possible to manually (well with a GPIO) control HDMI PLL power ON/OFF by unsoldering R2A9 and soldering it on R2A10 footprint.

Saluti,
Ale

On this same topic, the Jetson TK1 schematic has +3.3V_RUN connected to AVDD_HDMI via the backdrive circuit. The Tegra K1 Embedded Design Guide recommends +3.3V_RUN as well, but the Power Tree diagram in Section 2, Figure 1 needs to be updated.

Thanks MoonJP for the reminding. It had been updated in latest version. https://developer.nvidia.com/embedded/dlc/tegrak1-embedded-design-guide

Trumany, As of Embedded Design Guide version 08 (dated July 2016), the Power tree diagram is incorrect. Go to page 8, AVDD_HDMI is connected to +3.3V_LP0, not the recommend +3.3V_RUN.

Yes, you are right, will update it to latest version. Thanks.