Clock Frequency of pll_dp can only scale down and not scale up than 12MHz

Clock pll_dp has current input rate of 12MHz, since the source of the crystal is 12MHz. I want to scale up the pll_dp i.e. multiply above 12MHz. How do I do that? I see only dividers and not multipliers in the kernel code.

I’m not familiar with the particular PLL, but a PLL locks output phase to input phase. If it turns out that the output was measured by dividing the output by two, then the output must double in order to match phase. Division is multiplication.

Hi Kart,

Please check the chapter 5.0, ‘Clock and Reset Controller’, in TK1 OEM DG, there are detail instruction of divider/multiplier.