Codec integration (MAX98089) issues

Hi Joe,

Thanks for the update and sorry for the delay, I was out of office last week. I am surprised you are not seeing the LRCLK signal. What did you replace it with?

With regard to regmap, the sysfs location you should check if under …

ls /sys/kernel/debug/regmap/…

Try …

find /sys/kernel/debug/regmap/ | grep max980088

Jon

Hi Jon,

I am afraid i did not make myself clear. I replaced the Jetson SDK I was working with. The LRCLK signal was present on the new SDK and things worked as expected, once the amixer settings file was added with the appropriate routes. Thanks for the help.

Joe

Hi Joe,

I see, thanks for clarifying. Yes probably be best to best on the latest SDK. Is it rel28.1? We should be releasing rel28.2 and there are several audio related fixes in this (which will be described in the release notes). Not to say that rel28.1 will not work, but there have been a few things we have been fixing to improve the audio support (for things like TDM modes and 32-bit audio).

Regards,
Jon

Hi Jon,

I also have a problem recording audio on tx2 & max98090. I used sdk r32.1.
Sorry for that I don’t know how to attach image, so I just briefly describe the hardware of audio input:
“1 differential input connecting to IN1/IN2,and 1 mic input connecting to IN3/IN4” on my board.

I defined the routing in device tree as follow:

"x MIC1",  "x Mic",
"x MIC2",  "x Mic",
"x IN12",  "x Lin",

"x Hp",  "x HPR",
"x Hp",  "x HPL",
"x Lout",  "x RCVR",
"x Lout",  "x RCVL";

and in machine driver as follow:

SND_SOC_DAPM_HP("x Hp", NULL),
SND_SOC_DAPM_MIC("x Mic", NULL),
SND_SOC_DAPM_LINE("x Lin", NULL),
SND_SOC_DAPM_LINE("x Lout", NULL),

I tested mic input with the follow commands:

nvidia@nvidia-desktop:~$ amixer -c tegrasndt186ref cset name='x Left ADC Mixer MIC2 Switch' on
nvidia@nvidia-desktop:~$ amixer -c tegrasndt186ref cset name='x Right ADC Mixer MIC2 Switch' on
nvidia@nvidia-desktop:~$ amixer -c tegrasndt186ref  cset name=“ADMAIF3 Mux” I2S1
nvidia@nvidia-desktop:~$ arecord -D hw:tegrasndt186ref,2 -r 44100 -c 2 -f S16_LE <outputfile.wav>

and tested differential input with the follow commands:

nvidia@nvidia-desktop:~$ amixer -c tegrasndt186ref cset name='x Left ADC Mixer IN12 Switch' on
nvidia@nvidia-desktop:~$ amixer -c tegrasndt186ref cset name='x Right ADC Mixer IN12 Switch' on
nvidia@nvidia-desktop:~$ amixer -c tegrasndt186ref  cset name=“ADMAIF3 Mux” I2S1
nvidia@nvidia-desktop:~$ arecord -D hw:tegrasndt186ref,2 -r 44100 -c 2 -f S16_LE <outputfile.wav>

I could detect the aud_mclk & i2s_clk by OSC when recording, but I could not hear anything by “aplay <outputfile.wav>”.
I had verified the headphone & lineout on max98090 work properly.
Did I miss any “amixer” command when recording?

Thank you.

hi,

It looks like you need to add amixer commands to activate differential input. Hint, check the value of register 47 on the codec. If you are using the default codec driver, those controls might be missing.

BR

joe

Hi Joe,

Thank you for replying.

I thought the combination of the following commands and the modification I made in dts & drivers would activate differential input.

amixer -c tegrasndt186ref cset name='x Left ADC Mixer MIC2 Switch' on
amixer -c tegrasndt186ref cset name='x Right ADC Mixer MIC2 Switch' on

Could you tell me miss which “amixer” commands I should execute?
Thanks.

Hi,

the commands in your comment setup the mixer switch. They do not enable differential input. I don’t have access to the MAX98090 datasheet, but the MAX98089 is pretty similar and the driver did not have a control to set differential input on/off. I added it. That is why I cant sent you a command, because the control does not exist within the codec driver. I checked the source code for MAX98090 and I cant see one, but since, I don’t have the datasheet I am not sure which register they use for that purpose.
If you have a development board, setup the audio path the way you want it, make sure you have audio coming in and dump the register contents of the codec in a file. The dev board comes with a graphical application that allows you to setup the codec. Then use i2cget on your target board, after you apply the amixer settings, to verify that the codec register contents match. If you spot any differences, check the datasheet for those registers and figure out what are these differences affect.
For MAX98089, register 47 is responsible for turning differential input on/off for a specific port. Check if it is the same for MAX98090.

BR

joe

Hi Joe,

I’ve found the max98089 datesheet.
And as you said, the reg.0x47 is for differential inputs enable.
However, I didn’t found the register with the same description in max98090 datesheet. I guess that the input enable config is divided into reg.0x10/0x11(for mic1/mic2) and reg.0x3e(for line) according to the max98090 datesheet.

And I’ve check the registers by “i2cset” while recording, the relevant flag bits are all set.

Have you ever had the problem that no error happens in executing the amixer & arecord commands, but the date of recording wav file was all 0x00 except file header?

Hello!

Sorry for the delay. Another user was using this codec recently and we found that to get the Line inputs to work we needed to set the following …

$ amixer -c tegrasndt186ref cset name='x Left ADC Mixer LINEA Switch' on
$ amixer -c tegrasndt186ref cset name='x Right ADC Mixer LINEB Switch' on
$ amixer -c tegrasndt186ref cset name='x LINEA Mixer IN1 Switch' on
$ amixer -c tegrasndt186ref cset name='x LINEB Mixer IN2 Switch' on

Can you try enabling the LineA/B Mixer switches above as well?

Regards
Jon

Hi Jon,

Thank you for replying.

I’ll try as you say. But I’m a little confused: the commands you just mentioned seem to be for single-ended input, while my hardware was designed as one mic-input(IN3/IN4) and one differential input(IN1/IN2).

Have any other user designed the hardware similar to mine?
If yes, have any one record audio successfully?

Hi,

so you have verified that you get sound on the maxim devboard and that the registers match the register setup on your target board?
Does the .wav file have a size? Can you play it under windows i.e. not using aplay?

J

Hello!

Yes I was just passing on some information for getting the Line inputs working which I had come across recently. If this works for the Line inputs, then hopefully, may help you figure out how to enable the Mic inputs as well.

I do know that some of the Google chromebooks (Nyan) [0] use the MAX98090 and I believe use both the IN1/2 and IN3/4. There is some configuration for the Google Nyan in the ALSA library [1]. Otherwise, I recommend that you ask Maxim because they will have a much better insight to this codec.

Regards,
Jon

[0] http://dev.chromium.org/chromium-os/developer-information-for-chrome-os-devices/acer-cb5-311-chromebook-13
[1] https://git.alsa-project.org/?p=alsa-lib.git;a=blob;f=src/conf/ucm/GoogleNyan/HiFi.conf;h=b28fe917162dc31656a18e5758622178faf7659d;hb=HEAD

Hello!

Personally, I do not have a Maxim dev board with this codec on that I can connect to any of the Jetson platforms. However, I do know of people using this codec and have it working.

Regards,
Jon

hi,

I am not implying that it does not work. It is not straight forward to figure out the alsa commands. Personally, I bought a dev board, used the graphical tool under windows and setup the audio path so that I could record audio. Then, I dumped the register contents in a file. I then compared that file with the registers on my TX2 SDK when I connected the maxim devboard and I figured out which registers where not set and added the appropriate ALSA commands.

BR

Joe

Hi Joe,

Yes that is very true. I often find that the biggest hurdle to getting an I2S audio codec to work is understanding the codec audio paths and figuring out what mixer controls to set in order to configure and enable the audio path within the codec. So I do recommend that people check with either the codec vendor or the Linux/ALSA community to see if there are good examples for using a given audio codec with Linux.

There are some that we do test with and can offer guidance, but at the same time we don’t want to favour any specific I2S codec.

Regards,
Jon

Hi Jon,

Thank you very much.

I’m also in contact with the FAE of Maximum.
According to the reply from Maximum, I’ve got the BCLK & LRCLK signals and SDOUT from max98090 during recording. However, the data recording on tx2 is all 0x00.

It doesn’t seem to cause by mixer controls setting. Is it my modification in devicetree or driver error?

Hello!

Can you share the output from the following …

sudo cat /sys/kernel/debug/tegra_gpio
sudo grep dap1 /sys/kernel/debug/tegra_pinctrl_reg

It is possible the pins are not configured correctly, but otherwise it should work.

Regards,
Jon

Hi Jon,

the output of the commands is as follow:

Port:Pin:ENB DBC IN OUT_CTRL OUT_VAL INT_CLR
A:0 0x0 0x0 0x0 0x1 0x0 0x0
A:1 0x0 0x0 0x0 0x1 0x0 0x0
A:2 0x0 0x0 0x0 0x1 0x0 0x0
A:3 0x0 0x0 0x0 0x1 0x0 0x0
A:4 0x0 0x0 0x0 0x1 0x0 0x0
A:5 0x0 0x0 0x0 0x1 0x0 0x0
A:6 0x0 0x0 0x0 0x1 0x0 0x0
B:0 0x0 0x0 0x0 0x1 0x0 0x0
B:1 0x0 0x0 0x0 0x1 0x0 0x0
B:2 0x0 0x0 0x0 0x1 0x0 0x0
B:3 0x0 0x0 0x0 0x1 0x0 0x0
B:4 0x3 0x0 0x0 0x0 0x1 0x0
B:5 0x1 0x0 0x0 0x1 0x0 0x0
B:6 0x3 0x0 0x0 0x0 0x0 0x0
C:0 0x1 0x0 0x1 0x1 0x0 0x0
C:1 0x0 0x0 0x0 0x1 0x0 0x0
C:2 0x0 0x0 0x0 0x1 0x0 0x0
C:3 0x0 0x0 0x0 0x1 0x0 0x0
C:4 0x0 0x0 0x0 0x1 0x0 0x0
C:5 0x0 0x0 0x0 0x1 0x0 0x0
C:6 0x0 0x0 0x0 0x1 0x0 0x0
D:0 0x0 0x0 0x0 0x1 0x0 0x0
D:1 0x0 0x0 0x0 0x1 0x0 0x0
D:2 0x0 0x0 0x0 0x1 0x0 0x0
D:3 0x0 0x0 0x0 0x1 0x0 0x0
D:4 0x0 0x0 0x0 0x1 0x0 0x0
D:5 0x0 0x0 0x0 0x1 0x0 0x0
E:0 0x0 0x0 0x0 0x1 0x0 0x0
E:1 0x0 0x0 0x0 0x1 0x0 0x0
E:2 0x0 0x0 0x0 0x1 0x0 0x0
E:3 0x0 0x0 0x0 0x1 0x0 0x0
E:4 0x0 0x0 0x0 0x1 0x0 0x0
E:5 0x0 0x0 0x0 0x1 0x0 0x0
E:6 0x0 0x0 0x0 0x1 0x0 0x0
E:7 0x0 0x0 0x0 0x1 0x0 0x0
F:0 0x0 0x0 0x0 0x1 0x0 0x0
F:1 0x0 0x0 0x0 0x1 0x0 0x0
F:2 0x0 0x0 0x0 0x1 0x0 0x0
F:3 0x0 0x0 0x0 0x1 0x0 0x0
F:4 0x0 0x0 0x0 0x1 0x0 0x0
F:5 0x0 0x0 0x0 0x1 0x0 0x0
G:0 0x0 0x0 0x0 0x1 0x0 0x0
G:1 0x0 0x0 0x0 0x1 0x0 0x0
G:2 0x0 0x0 0x0 0x1 0x0 0x0
G:3 0x0 0x0 0x0 0x1 0x0 0x0
G:4 0x0 0x0 0x0 0x1 0x0 0x0
G:5 0x0 0x0 0x0 0x1 0x0 0x0
H:0 0x0 0x0 0x0 0x1 0x0 0x0
H:1 0x0 0x0 0x0 0x1 0x0 0x0
H:2 0x0 0x0 0x0 0x1 0x0 0x0
H:3 0x0 0x0 0x0 0x1 0x0 0x0
H:4 0x3 0x0 0x0 0x0 0x1 0x0
H:5 0x3 0x0 0x0 0x0 0x0 0x0
H:6 0x3 0x0 0x0 0x0 0x0 0x0
I:0 0x0 0x0 0x0 0x1 0x0 0x0
I:1 0x0 0x0 0x0 0x1 0x0 0x0
I:2 0x0 0x0 0x0 0x1 0x0 0x0
I:3 0x0 0x0 0x0 0x1 0x0 0x0
I:4 0x1 0x0 0x1 0x1 0x0 0x0
I:5 0x1 0x0 0x0 0x1 0x0 0x0
I:6 0x1 0x0 0x0 0x1 0x0 0x0
I:7 0x1 0x0 0x0 0x1 0x0 0x0
J:0 0x1 0x0 0x0 0x1 0x0 0x0
J:1 0x1 0x0 0x0 0x1 0x0 0x0
J:2 0x1 0x0 0x0 0x1 0x0 0x0
J:3 0x1 0x0 0x0 0x1 0x0 0x0
J:4 0x1 0x0 0x0 0x1 0x0 0x0
J:5 0x49 0x0 0x1 0x1 0x0 0x0
J:6 0x1 0x0 0x1 0x1 0x0 0x0
J:7 0x0 0x0 0x0 0x1 0x0 0x0
K:0 0x0 0x0 0x0 0x1 0x0 0x0
L:0 0x0 0x0 0x0 0x1 0x0 0x0
L:1 0x0 0x0 0x0 0x1 0x0 0x0
L:2 0x0 0x0 0x0 0x1 0x0 0x0
L:3 0x0 0x0 0x0 0x1 0x0 0x0
L:4 0x3 0x0 0x0 0x0 0x0 0x0
L:5 0x3 0x0 0x0 0x0 0x0 0x0
L:6 0x0 0x0 0x0 0x1 0x0 0x0
L:7 0x0 0x0 0x0 0x1 0x0 0x0
M:0 0x0 0x0 0x0 0x1 0x0 0x0
M:1 0x0 0x0 0x0 0x1 0x0 0x0
M:2 0x0 0x0 0x0 0x1 0x0 0x0
M:3 0x0 0x0 0x0 0x1 0x0 0x0
M:4 0x3 0x0 0x0 0x0 0x1 0x0
M:5 0x45 0x0 0x1 0x1 0x0 0x0
N:0 0x3 0x0 0x0 0x0 0x1 0x0
N:1 0x0 0x0 0x0 0x1 0x0 0x0
N:2 0x3 0x0 0x0 0x0 0x0 0x0
N:3 0x1 0x0 0x0 0x1 0x0 0x0
N:4 0x1 0x0 0x0 0x1 0x0 0x0
N:5 0x1 0x0 0x0 0x1 0x0 0x0
N:6 0x1 0x0 0x1 0x1 0x0 0x0
O:0 0x0 0x0 0x0 0x1 0x0 0x0
O:1 0x0 0x0 0x0 0x1 0x0 0x0
O:2 0x0 0x0 0x0 0x1 0x0 0x0
O:3 0x0 0x0 0x0 0x1 0x0 0x0
P:0 0x0 0x0 0x0 0x1 0x0 0x0
P:1 0x4d 0x0 0x0 0x1 0x0 0x0
P:2 0x0 0x0 0x0 0x1 0x0 0x0
P:3 0x3 0x0 0x0 0x0 0x0 0x0
P:4 0x1 0x0 0x1 0x1 0x0 0x0
P:5 0x4d 0x0 0x1 0x1 0x0 0x0
P:6 0x3 0x0 0x0 0x0 0x0 0x0
Q:0 0x0 0x0 0x0 0x1 0x0 0x0
Q:1 0x0 0x0 0x0 0x1 0x0 0x0
Q:2 0x0 0x0 0x0 0x1 0x0 0x0
Q:3 0x0 0x0 0x0 0x1 0x0 0x0
Q:4 0x0 0x0 0x0 0x1 0x0 0x0
Q:5 0x0 0x0 0x0 0x1 0x0 0x0
R:0 0x3 0x0 0x0 0x0 0x0 0x0
R:1 0x3 0x0 0x0 0x0 0x0 0x0
R:2 0x3 0x0 0x0 0x0 0x0 0x0
R:3 0x3 0x0 0x0 0x0 0x0 0x0
R:4 0x3 0x0 0x0 0x0 0x1 0x0
R:5 0x3 0x0 0x0 0x0 0x0 0x0
T:0 0x0 0x0 0x0 0x1 0x0 0x0
T:1 0x0 0x0 0x0 0x1 0x0 0x0
T:2 0x1 0x0 0x1 0x1 0x0 0x0
T:3 0x1 0x0 0x0 0x1 0x0 0x0
X:0 0x0 0x0 0x0 0x1 0x0 0x0
X:1 0x0 0x0 0x0 0x1 0x0 0x0
X:2 0x0 0x0 0x0 0x1 0x0 0x0
X:3 0x0 0x0 0x0 0x1 0x0 0x0
X:4 0x0 0x0 0x0 0x1 0x0 0x0
X:5 0x0 0x0 0x0 0x1 0x0 0x0
X:6 0x3 0x0 0x0 0x0 0x0 0x0
X:7 0x4d 0x0 0x0 0x1 0x0 0x0
Y:0 0x1 0x0 0x1 0x1 0x0 0x0
Y:1 0x1 0x0 0x1 0x1 0x0 0x0
Y:2 0x1 0x0 0x1 0x1 0x0 0x0
Y:3 0x0 0x0 0x0 0x1 0x0 0x0
Y:4 0x3 0x0 0x0 0x0 0x1 0x0
Y:5 0x1 0x0 0x1 0x1 0x0 0x0
Y:6 0x1 0x0 0x0 0x1 0x0 0x0
BB:0 0x3 0x0 0x0 0x0 0x0 0x0
BB:1 0x3 0x0 0x0 0x0 0x0 0x0
CC:0 0x0 0x0 0x0 0x1 0x0 0x0
CC:1 0x0 0x0 0x0 0x1 0x0 0x0
CC:2 0x0 0x0 0x0 0x1 0x0 0x0
CC:3 0x0 0x0 0x0 0x1 0x0 0x0
Bank: 0 Reg: 0x02431028 Val: 0x00000055 -> dap1_fs_pj3
Bank: 0 Reg: 0x02431030 Val: 0x00000055 -> dap1_din_pj2
Bank: 0 Reg: 0x02431038 Val: 0x00000055 -> dap1_dout_pj1
Bank: 0 Reg: 0x02431040 Val: 0x00000055 -> dap1_sclk_pj0

I guess just the follow values need to be looked at:

Port:Pin:ENB DBC IN OUT_CTRL OUT_VAL INT_CLR
J:   0   0x1 0x0 0x0 0x1     0x0     0x0
J:   1   0x1 0x0 0x0 0x1     0x0     0x0
J:   2   0x1 0x0 0x0 0x1     0x0     0x0
J:   3   0x1 0x0 0x0 0x1     0x0     0x0

Does this prove that the sdin pin is configured as output?
If so, how can I modify it?

Hello!

Yes so this shows that the pins are no configured correctly for I2S. What L4T release are you using?

Regards,
Jon

Hi Jon,

Thank you.

I’m using L4T release r32.1,