Concern about Pin Schematics

Hi,
I’m actually preparing a PCB for the Jetson Nano. However, I found an incoherence between the Jetson Nano Pinmux Table (https://developer.nvidia.com/embedded/dlc/jetson-nano-pinmux-table) and the schematics (https://developer.nvidia.com/embedded/dlc/Jetson-Nano-Carrier-Board-Reference-Design-Files). Pin 2 in the schematics is defined as GND but in the table is CSI1_D0_N. Did I miss a detail?
Thx in advance!

Hi, we are checking this, will update later, thanks.

Hi, the latest pinmux has fixed this. https://developer.nvidia.com/jetson-nano-pinmux