Hi!
I have custom a carrier board and an Intel Max 10 FPGA is connected on SPI0 and I dont know how to config in the device tree. I found the driver source “intel-m10-bmc.c”. Is its right?
Thank you so much
Hi viet1.lehung,
Are you using the devkit or custom board for AGX Orin?
What’s your Jetpack version in use?
Have you asked your vendor for the porting guide of FPGA module?
Hi @KevinFFF , thank you for your response
I’m using the custom board with SOM jetson orin nano 8GB, Jetpack 6.0.
I can not find any guide from the vender
I’ going to config as the bellow, is it right?
spi@3210000{
status = "okay";
spi@0 {
compatible = "microchip,mcp2515";
reg = <0x0>;
spi-max-frequency = <2000000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA234_MAIN_GPIO(Q, 5) IRQ_TYPE_LEVEL_LOW>;
clocks = <&can_clock>;
nvidia,enable-hw-based-cs;
controller-data {
nvidia,enable-hw-based-cs;
nvidia,rx-clk-tap-delay = <0x10>;
nvidia,tx-clk-tap-delay = <0x0>;
};
fpga@0 {
compatible = "intel, intel-m10-bmc";
spi-max-frequency = <20000000>;
reg = <0>;
}
};
Please also contact your vendor for those resources. There should be some documentation for how to use them.
It would cause conflict for SPI0-CS0 since spi@0
and fpga@0
are both defining for SPI0-CS0.
Please just keep one of them.
Our FPGA is connected as in this image
May I remove the fpga node? Because the FPGA has been pre programmed by the vendor. We have enable the FPGA board management control in the kernel config.
Yes, I think FPGA is redundant in above connections.
Please connect SPI-CAN on SPI interface.
Are you using something like MCP2515 or MCP2518 as SPI-CAN module?
And connect CAN transceiver on internal CAN interface (CAN0 and CAN1 are available on 40-pins expansion header).
This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.