Configure DMA with uarte(HSUART) on Jetson Orin with JetPack 6.2

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

Hi Jetson Team,

I am currently working with the High-Speed UART (HSUART) driver and attempting to optimize performance using DMA. Despite updating my device tree (.dtsi) to enable DMA for the uarte(serial@3140000) node, I am unable to achieve a stable baud rate of 921600 bps.

Below is the configuration I am using:

DTS

serial@3140000 {
    compatible = "nvidia,tegra194-hsuart";
    reg = <0x00 0x3140000 0x00 0x10000>;
    interrupts = <0x00 0x74 0x04>;
    clocks = <0x03 0x9f>;
    resets = <0x03 0x68>;
    dmas = <0xee 0x14 0xee 0x14>;
    dma-names = "rx", "tx";
    status = "okay";
    reset-names = "serial";
    phandle = <0x22c>;
};

How to enable DMA with uarte as hsuart(ttyTHS3)?
Additionally, are there specific clock frequency requirements or kernel configurations I need to adjust to support this high-speed rate reliably?

2

*** Please note that this reply is generated by LLM automatically ***

To enable DMA with uarte as hsuart/ttyTHS3, you need to make several changes to your device tree configuration. Here’s a step-by-step guide to help you achieve this:

  1. Enable DMA in the device tree: You’ve already updated your device tree to enable DMA for the uarte node. Ensure that the dma-names property is set to “rx” and “tx” for the uarte node, and the dma property is set to the DMA channel number.

Example:

&uarte {
    dma-names = "rx", "tx";
    dma = <&dma 0>;
};
  1. Configure the DMA channel: You need to configure the DMA channel to use the correct DMA controller and channel number. The DMA controller and channel number may vary depending on your Jetson module.

For Jetson AGX Orin, you can use the following configuration:

&dma {
    compatible = "nvidia,tegra186-dma";
    dma-channels = <32>;
    dma-requests = <32>;
    dma-masters = <&uarte>;
};
  1. Set the clock frequency: To achieve a stable baud rate of 921600, you need to ensure that the clock frequency is set correctly. The clock frequency required for this baud rate is 921600 Hz.

You can set the clock frequency using the clock-frequency property in the device tree.

Example:

&uarte {
    clock-frequency = <921600>;
};
  1. Configure the kernel: To support high-speed UART rates, you need to configure the kernel to use the correct UART driver and settings.

You can configure the kernel by adding the following lines to your kernel configuration file (e.g., config.txt):

CONFIG_UART_TEGRA=y
CONFIG_UART_TEGRA_HSUART=y
CONFIG_UART_TEGRA_HSUART_DMA=y
  1. Verify the configuration: After making these changes, verify that the DMA is enabled and the clock frequency is set correctly using the following commands:
cat /sys/kernel/debug/tegra_uart/dma_status
cat /sys/kernel/debug/tegra_uart/clock_frequency

If you’re still experiencing issues, you can try adjusting the DMA buffer size or the UART FIFO size to optimize performance.

Comparison with other Jetson modules:

The configuration steps above are specific to Jetson AGX Orin. If you’re using a different Jetson module, you may need to adjust the DMA controller and channel number, as well as the clock frequency.

Here’s a comparison of the DMA configuration for different Jetson modules:

Jetson Module DMA Controller DMA Channel Number Clock Frequency
Jetson AGX Orin nvidia,tegra186-dma 0 921600 Hz
Jetson Xavier NX nvidia,tegra194-dma 0 921600 Hz
Jetson TX2 nvidia,tegra186-dma 1 921600 Hz

Note that these values are specific to the UART driver and may vary depending on the specific use case and configuration.

*** Please give the thumbs up if you get answers you like. Or provide feedback to help us improve the answer. ***

4

Hi vrushti.dabhi,

Are you using the devkit or custom board for AGX Orin?

To enable DMA-based UART, you can just add appropriate dma related properties in device tree.

Could you share the full dmesg and device tree for further check.

5

Hi KevinFFF,

I am using a custom board for AGX ORin.

Attached here the complete dmesg and dts.

dmesg.txt (70.9 KB)

kernel_tegra234-p3737-0000+p3701-0004-nv.dts.txt (322.5 KB)

6

With dma enabled on uart4 getting below error logs in dmesg

[  730.647698] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[  730.647759] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803000, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  730.647826] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: VPR violation ((null))
[  730.647828] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[  730.647900] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xfc011040, fsynr=0x6c0002, cbfrsynra=0xc04, cb=0
[  730.647963] tegra-mc 2c00000.memory-controller: unknown: secure read @0x000000ffffffff00: EMEM address decode error (EMEM decode error)
[  730.647966] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: VPR violation ((null))
[  730.647969] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[  730.648034] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803000, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  730.648165] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803000, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  730.648287] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803040, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  730.648424] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803040, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  730.648548] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803040, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  730.648683] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80803040, fsynr=0x6c0011, cbfrsynra=0x804, cb=0
[  739.860906] nvidia_smmu_context_fault_bank: 28 callbacks suppressed
[  739.860919] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xfc013000, fsynr=0x210002, cbfrsynra=0x404, cb=0
[  739.861040] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80801000, fsynr=0x210011, cbfrsynra=0x4, cb=0
[  739.861159] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80801000, fsynr=0x210011, cbfrsynra=0x4, cb=0
[  739.861277] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80801000, fsynr=0x210011, cbfrsynra=0x4, cb=0
[  739.861395] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80801000, fsynr=0x210011, cbfrsynra=0x4, cb=0
[  739.861513] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80801000, fsynr=0x210011, cbfrsynra=0x4, cb=0
[  739.861631] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x80801000, fsynr=0x210011, cbfrsynra=0x4, cb=0
[  739.863335] tegra30_mc_handle_irq: 34 callbacks suppressed
[  739.863338] tegra-mc 2c00000.memory-controller: unknown: secure read @0x000000ffffffff00: EMEM address decode error (EMEM decode error)
[  739.863345] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: VPR violation ((null))
[  739.863351] tegra-mc 2c00000.memory-controller: unknown: secure write @0x00000003ffffff00: Route Sanity error ((null))
[  739.863419] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0xfc013040, fsynr=0x210002, cbfrsynra=0x404, cb=0
7

Hi @KevinFFF , can you help me with the configuration?

8

It seems you missing iommus property for this UART interface.
Could you try adding it as following to check if it could help for your case?

serial@3140000 {
    compatible = "nvidia,tegra194-hsuart";
    reg = <0x00 0x3140000 0x00 0x10000>;
    interrupts = <0x00 0x74 0x04>;
    clocks = <0x03 0x9f>;
    resets = <0x03 0x68>;
    dmas = <0xee 0x14 0xee 0x14>;
    dma-names = "rx", "tx";
+   iommus = <0x04 0x04>;
    status = "okay";
    reset-names = "serial";
    phandle = <0x22c>;
};