Configure fsync data offset for i2s (2 bit delay)

[loic.boileau]

Hi!

I’m back for (probably) my last question!

I’m currently trying to configure the i2s and everything’s working fine except the FSYNC OFFSET which i can’t seem to be able to change usign amixer API. Using the dsp-a codec mode, we can have a 1-bit delay but we need a 2-bit delay. So my thoughts are to go directly inside the register fields controlling the offset.

For I2S1 as an example, the address is 0x02901000 and the offset following the TRM is 0x24: [for now, I cant seem to be able to add an image…]

So maybe i should just use busybox devmem 0x02901024 w 0x00000200 (since data offset are located at bit 18:8)?

What do you think?

Thank you and have a great week!

Loic

[Sheetal.G]

Hi,
Directly updating the value in register is not recommended.
If you want 2-bit delay for dsp-a codec mode, please apply below change in I2S driver

diff --git a/sound/soc/tegra/tegra210_i2s.c b/sound/soc/tegra/tegra210_i2s.c
index cc0833ef42e9..496f600c1868 100644
--- a/sound/soc/tegra/tegra210_i2s.c
+++ b/sound/soc/tegra/tegra210_i2s.c
@@ -236,7 +236,7 @@ static int tegra210_i2s_set_fmt(struct snd_soc_dai *dai,
        case SND_SOC_DAIFMT_DSP_A:
                val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;
                val |= I2S_CTRL_LRCK_POL_HIGH;
-               tegra210_i2s_set_data_offset(i2s, 1);
+               tegra210_i2s_set_data_offset(i2s, 2);
                break;
        case SND_SOC_DAIFMT_DSP_B:
                val |= I2S_CTRL_FRAME_FMT_FSYNC_MODE;

[loic.boileau]

I did the modification but when running busybox devmem 0x02901024 I still get 0x00000100 which means data offset is 1 and not 2…

This is the steps I did:

1. Modify the kernel file like mentionned with offset of 2 for dsp-a mode
2. Recompile kernel with sudo ./nvbuild.sh
3. Copy the kernel files and Image to BSP :

sudo cp sources/kernel/kernel-5.10/drivers/gpu/nvgpu/nvgpu.ko rootfs/usr/lib/modules/5.10.104-tegra/kernel/drivers/gpu/nvgpu/nvgpu.ko 
 
cp -R sources/kernel/kernel-5.10/arch/arm64/boot/dts/nvidia/. kernel/dtb 
 
cp sources/kernel/kernel-5.10/arch/arm64/boot/Image kernel/Image 

4. Reflash completly the jetson : sudo ./flash.sh jetson-agx-orin-devkit mmcblk0p1

Is there a way to check the modification has been correctly done, like a print inside the kernel or a dts file to check?

Thanks!

Loic

[Sheetal.G]

Yes you can add a print like below:

pr_info("Data offset 2 for dsp-a format\n");
tegra210_i2s_set_data_offset(i2s, 2);

[loic.boileau]

Hi,

I added the print line to the kernel, followed the same building steps as before and nothing appears in both flash.log and dmesg.log. I tried modifying i2s codec function using alsamixer but it did not print the “Data offset” line.

What are the next steps to figure out why it does not change the register for data offset?

Loic

[Sheetal.G]

If print is not observed that means the modified i2s driver is not flashed.
I2S driver is a module, did you modify it to be part of kernel image itself?
If not, please make sure to update the *.ko module.

Also, please note that the print will be available only if you are setting the I2S format to dsp_a.
If still it doesn’t work please share the mixer settings.

[loic.boileau]

It did work, I just needed to switch the .ko driver!

Thank you a lot for your help!