Configuring the UPHY Lane

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin NX
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Hi NVIDIA Team,

I’m currently configuring the Orin NX UPHY Lane. The documentation shows this table:

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However it’s not completely clear to me the two configurations. The first option is to use CSI4_D[0:2]_RX0_TX0 and CSI4_D[1:3]_RX1_TX1 as one (PCIE x2)?
And the second option is to use CSI4_D[0:2]_RX0_TX0 and CSI4_D[1:3]_RX1_TX1separately as two PCIE x1?

Thanks.

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please refer to the design guide document. It shall be more clear.

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