On a custom carrier-board, I have two type-c connectors, wired to DP0 and DP1.
DP0 works fine, but debugging a problem related to DP1 has raised a question:
- How the DP1_HPD (GPIO M.1) pin is configured as DP hotplug input?
- Is the configuration done only by kernel device tree or does it include something the drivers or bootloader do?
The intention is to configure both outputs as similar DP outputs.
The kernel device tree changes that I have tried are included at the end of this message.
According to Xavier NX pinmux excel-sheet, the inputs DP0_HPD and DP1_HPD equal GPIOs M0 and M1.
State of those GPIOs can be read from/sys/kernel/debug/tegra_gpio:
Port:Pin:ENB DBC IN OUT_CTRL OUT_VAL INT_CLR
...
M:0 0x0 0x0 0x0 0x1 0x0 0x0
M:1 0x1 0x0 0x0 0x0 0x0 0x0
I can see the IN value of DP1_HPD (GPIO M.1) changing when cable is plugged or removed to DP1, as expected (when the pin is in GPIO mode).
The DP0_HPD (GPIO M.0) input state does not seem to change when plugging the cable, but maybe it’s because the pin is configure to something else than GPIO?
I noticed that the M.1 (DP1_HPD) ENB value changed from 0x4d to 0x1 after I made the attached changes in the device tree. I have no idea how to get similar change in M.0. Changing the head0 and head1 configurations to match does not change the M.0 gpio values.
Device tree changes
I have made the following changes to the device tree:
nvidia/platform/t19x/jakku/kernel-dts/common/tegra194-p3509-disp.dtsi
(only modified entries are shown here, others are as defaults)
&head0 {
status = "okay";
nvidia,fb-bpp = <32>;
nvidia,fbmem-size = <265420800>; /* 8K (7680*4320) 32bpp double buffered */
nvidia,fb-flags = <TEGRA_FB_FLIP_ON_PROBE>;
win-mask = <0x7>;
nvidia,fb-win = <0>;
nvidia,dc-connector = <&sor1>;
nvidia,dc-flags = <TEGRA_DC_FLAG_ENABLED>;
avdd_hdmi-supply = <&p3668_spmic_sd0>; /* 1v0 */
avdd_hdmi_pll-supply = <&p3668_spmic_sd1>; /* 1v8 */
vdd_hdmi_5v0-supply = <&p3509_vdd_hdmi_5v0>; /* 5v0 */
//Added the following 2 lines to match the configuration with head1 (that works)
avdd-dp-pll-supply = <&p3668_spmic_sd1>;
vdd-edp-sec-mode-supply = <&battery_reg>;
};
&sor0 {
status = "okay";
nvidia,active-panel = <&sor0_dp_display>;
};
&sor0_dp_display {
status = "okay";
nvidia,is_ext_dp_panel = <1>;
};
&sor1 {
status = "okay";
//Changed active-panel to point dp display instead of hdmi and added the similar sor1_dp_display:
nvidia,active-panel = <&sor1_dp_display>;
};
&sor1_dp_display {
status = "okay";
nvidia,is_ext_dp_panel = <1>;
};
Also noticed that heads are “cross linked” head0->sor1 and head1->sor0 by default. Is there a specific reason for this?