Confused about CAN stuff: mttcan, mttcan-ivc and nvhvseccan - DRIVE 4.1.8.0

After setting up my DrivePX2 Chauffeur board with the latest 4.1.8.0 including the AURIX update 2.02 I checked for the CAN documentation and the common questions here in the forum.

I found this SDK documentation http://docs.nvidia.com/drive/nvvib_docs/index.html#page/NVIDIA%2520Vibrante%2520Linux%2520DPX%2520Development%2520Guide%2FAppendix%2FAppxTegraCAN.html%23 which only talks about mttcan configuration (and its weird - non standard - ID filter setup).

I checked the EasyCAN user guide from Elektrobit “EB-DrivePX_Software_User_Guide_DPX2.pdf” which can be not be found in the SDK docs (why not?) but somewhere deep in the installation files https://devtalk.nvidia.com/default/topic/1025162/drive-hardware/which-aurix-controller-is-available-on-px2/post/5214798/#5214798?!?

So I managed to get the two SocketCAN compatible interfaces on TegraA (can0) and TegraB (can1) working on CAN5/CAN6 of the harness (btw. did not find any documentation if these CAN busses are terminated with some resistor?). Are TegraA (can1) and TegraB (can0) connected anywhere?

For the access to CAN1-CAN4 via the AURIX-CPU from Linux, EB provides some code samples found in DPX2-P2379-EB-V2.02.04_release.zip at DPX2-P2379-EB-V2.02.04_release/bin/EB-DrivePX-Samples/AurixTegraCan/aurix_tegra.c . But this does not fit to my standard SocketCAN can-utils toolset with candump, cansend, canplayer which works like charm on TegraA can0. So there’s a break in CAN access APIs - a vendor lock-in for CAN applications which SocketCAN intended to solve.

Additionally the MTTCAN IP core from Bosch provides Time-Triggered (TT) CAN bus access, which is not mentioned in the SDK documentation at all.

Can you help on these questions …

  1. How can I use the time triggered functionality of the MTTCAN (examples/documentation)?
  2. Are TegraA (can1) and TegraB (can0) connected anywhere?
  3. Why are the bitrates (CAN/CAN FD) restricted in mttcan in comparison to the m_can driver in mainline Linux?
  4. What is the intention of mttcan-ivc driver module? Does it make AURIX CAN interfaces SocketCAN interfaces on the Tegra (which would be cool)? How can they be configured and used?
  5. What is the intention of nvhvseccan driver module? How can it be configured and used?

Thanks,
Oliver

Hi Oliver,

Here some answers to your questions (the answers are mostly taken from Vibrante for Linux documentation, as you pointed above http://docs.nvidia.com/drive/nvvib_docs/index.html in the CAN section):
1. How can I use the time triggered functionality of the MTTCAN (examples/documentation)?
Set up and usage of MTTCAN is as follows. You can set up the bitrate and restart time for time triggered functionality.

Usage: ip link set DEVICE type can 
        [ bitrate BITRATE [ sample-point SAMPLE-POINT] ] | 
        [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1 
          phase-seg2 PHASE-SEG2 [ sjw SJW ] ] 
  
        [ dbitrate BITRATE [ dsample-point SAMPLE-POINT] ] | 
        [ dtq TQ dprop-seg PROP_SEG dphase-seg1 PHASE-SEG1 
          dphase-seg2 PHASE-SEG2 [ dsjw SJW ] ] 
  
        [ loopback { on | off } ] 
        [ listen-only { on | off } ] 
        [ triple-sampling { on | off } ] 
        [ one-shot { on | off } ] 
        [ berr-reporting { on | off } ] 
        [ fd { on | off } ] 
  
        [ restart-ms TIME-MS ] 
        [ restart ] 
  
        Where: BITRATE  := { 1..1000000 } 
                  SAMPLE-POINT  := { 0.000..0.999 } 
                  TQ            := { NUMBER } 
                  PROP-SEG      := { 1..8 } 
                  PHASE-SEG1    := { 1..8 } 
                  PHASE-SEG2    := { 1..8 } 
                  SJW           := { 1..4 } 
                  RESTART-MS    := { 0 | NUMBER }

2. Are TegraA (can1) and TegraB (can0) connected anywhere?

Tegra-A and Tegra-B are inter-connected with Ethernet over the Marvell Gb AVB Switch. They can communicate with each another through this network connection.
Each Tegra is dynamically assigned an IP address at boot. Network configuration is managed by the systemd-networkd daemon. You can then use SCP to copy files between Tegras, use the socket API to have application communicate between the 2 Tegras etc.

3. Why are the bitrates (CAN/CAN FD) restricted in mttcan in comparison to the m_can driver in mainline Linux?

125000(125 Kbps), 250000(250 Kbps), 500000(500 Kbps) and 1000000(1Mbps) are supported bitrates for Tegra MTTCAN driver.
Any other bitrate is not validated on Tegra MTTCAN driver.
Only 500000 (500 Kbps) bitrate is supported for Tegra MTTCAN-IVC. Other bitrates are not enabled on Tegra MTTCAN-IVC driver out of box. Details are available in the SPE documentation.

4. What is the intention of mttcan-ivc driver module? Does it make AURIX CAN interfaces SocketCAN interfaces on the Tegra (which would be cool)? How can they be configured and used?
There are two implementation of MTTCAN SocketCAN driver:

  • mttcan driver that controls CAN controller directly through CPU running Linux
  • mttcan-ivc that uses CAN driver services through IVC and implemented in SPE-FW. This driver can potentially be used by both SPE firmware and Linux.

Regards,
Josep

Hi Josep,

thanks for your answers!

Sorry if I unclearly expressed myself. Of course I read the documentation and setting the bitrate is no problem for me.

The difference between the MCAN IP core and the MTTCAN IP core which is integrated in the Tegra SoC is the possibility to make the controller act as a time triggered master or slave node following ISO 11898-4 see e.g. https://en.wikipedia.org/wiki/Time-Triggered_Protocol .

So my question was about how to use this specific “time triggered” mode of the MTTCAN driver? Are there any examples/documentations?

I had a CAN related question, I’ll try to reorder:

  • Is can1 from Tegra A connected anywhere?
  • Is can0 from Tegra B connected anywhere?

I know this connection:

Tegra A can0 -> CAN5
Tegra B can1 -> CAN6

But Tegra A can1 and Tegra B can0 both seem not to be connected at all.

My question was WHY did you made these restrictions? IMO there’s no reason for that.

What means “SPE documentation”? Where can I find it?

I read this sentence in the documentation too. But I still don’t know how this Linux/SPE-FW setup looks like, whether it provides a SocketCAN interface on the Tegra and how I can make the mttcan-ivc driver WORK on a real CAN bus?

So in fact all my questions are still unanswered … :-/

Thanks & best regards,
Oliver

1 Like