Confusion about PullUp/DOwn resitors in PADCTL

[jost38]

Hello,
I am currently controlling PIN 7 from the 40Pin expansion header on the Orin AGX Devkit.
For that, I’m using the busybox devmem command to write to the specific pin registers.
General input and output work fine, but I’m having some trouble getting the pull-up resistor for input to work.
For normal input without pull resistor, I have set the following registers to these values:
PADCTL_G3_SOC_GPIO33_0 = 0x02430070 = 0x050 (gpio, input and tristate)
GPIO_Q_ENABLE_CONFIG_06_0 = 0x022426c0 = 0x01
GPIO_Q_OUTPUT_CONTROL_06_0 = 0x022426cc = 0x01
and I’m reading the value from the register:
GPIO_Q_INPUT_06_0 = 0x022426c8

This works however when I try to then set PADCTL 0x02430070 to 0x054 for a pull-down resistor,
the pin still reads high even after 3.3V are disconnected.

In which way do I have to set the register values to have a pull-down effect on the pin I’m reading?

[KevinFFF]

Hi jost38,

What’s the Jetpack version in use?

@jost38

In which way do I have to set the register values to have a pull-down effect on the pin I’m reading?

Pinmux register is used in MB1 so that you should configure them in pinmux spreadsheet and update the pinmux dtsi.
After flashing the board, it should take effect during boot up.

[jost38]

Hi,
I’m currently using Jetpack 5.1.
Do I understand it correctly that changing pullup/pulldown resistors is only possible through flashing the board, and not doable during runtime through the register values?

[KevinFFF]

@jost38

Do I understand it correctly that changing pullup/pulldown resistors is only possible through flashing the board, and not doable during runtime through the register values?

You can also write the register with the expected value but they are only valid before next reboot.
We would suggest just configuring from pinmux spreadsheet and flash the board to apply change.

[jost38]

The values resetting after every boot doesn’t matter.
But for my program I need either pull up/down pins depending on some inputs during runtime.
But I’m struggling with setting up the pinmux and gpio controller in the correct way to achieve pull down/up behavior.
Is there any other register setup required on the Orin AGX devkit to achieve resistor pulling on an input pin.
Or what could be the cause, I’m unable to verify the functionality.

[KevinFFF]

@jost38

ling PIN 7 from the 40Pin expansion header on the Orin AGX Dev

For PIN7 of 40pins expansion header, it is also known as PQ.06.

You can configure it in pinmux spreadsheet as following:

Pull-Up:

Pull-Down:

As my understanding, it is the only place that you need to configure for internal pulling.
You can just configure as above any check its default state after boot up.

[jost38]

So I went ahead and did that with the default values of the pinmux where Header Pin7 is set as input and pulldown.
And the register values are the same as I configured the before to achieve this.
PADCTL 0x54
ENABLE CONFIG = 0x01
OUT CONTROL = 0x01

However, even with the configuration done by the board, I still can’t observe a pulldown behavior.
When I connect the pin to GND of the 40Pin Header, it reads “0” in the GPIO_Q_INPUT_06_0 register.
And when I connect it afterward to 3.3V on the Header, it reads 1 in the register.
But the value in the register stays “1” even when the pin is not connected to anything anymore.
The value stays “1” until I connect the pin to GND again, when it changes to “0”.
So the is no pulldown effect happening at the pin.

[Trumany]

@jost38

But the value in the register stays “1” even when the pin is not connected to anything anymore.

You should probe the pin to check if the voltage level is still high. If it is high, then it could be the left floating voltage on level shift as you can see in the carrier board schematic.

[jost38]

I went ahead, probed the Pin, and it corresponded with the values in the register.
Meaning it was left floated and so still charged.
I checked the schematic (“P3737_A05_OrCAD_schematics(base_version)”), I hope is the correct one.
And yeah, it seems the level shifter overrides the pull down on the Orin Module.

Then I identified a pin that was directly connected to the Orin Module (Pin 16 on the 40Pin expansion header).
With this pin, I can measure the correct behavior for the values in the PADCTL register for pull up or down resistors.

But the Signals on the B Side of the Level Shifter are still connected to ground via a 1M resistor.
The datasheet of the level shifter mentions a pin capacitance of around 8pF.
So I think the Signal should still be pulled to low when nothing is connected, or am I missing something?

[Trumany]

No, you can wait for longer discharge time to check.

[jost38]

I measured the Voltage on the “floating” Pin, which was only connected to my oscilloscope probe. And even after 30 minutes, the Voltage remained exactly at 3.3V.
That seems like a way too high discharge time.
Also, when measured the time it takes to discharge 3.3V from the capacitance of the probe with its internal 10M resistor, it comes around at >1ms.
Since the Pin remains High for such a long time, it must be driven somehow.
My guess would be that the high Value pull down resistors on both sides are too weak and since it’s a bidirectional level shifter it seems that both sides drive each other in a feedback loop way.
Because both sides were driven and thus charged before the Pin was left floated, are not strong enough to be pulled to ground.
But I don’t have a way to verify that claim.

There also seem to be other people having the same Problem

Orin Jetson AGX Devkit GPIO Pull-up/Pull-down

I am currently working an NVIDIA Jetson AGX Orin Devkit. The issue I am experiencing is that the devkit gpio pins (40 pin header) do not properly pull down. Here is my setup: I have a SPST switch connected to header pin 7 (SOC_GPIO33 / GPIOPQ.06 / gpio-454). The switch is wired such that when the switch is “on”, the pin will go high (3.3V supplied to the pin). When the switch is “off”, it is wired with an external pull-down resistor. I am using Jetpack 5.1, since I read that previous versions…

My conclusion would be that when needing pull up/down resistors on the 40Pin Gpio Header, you either need to use as pin that is not connected through a level shifter or set up your own PCB to attach to the header from where you can set the resistors.

[Trumany]

Did you see same behavior on other pins of 40-pin header coming thru level shift on your board?
Is your setting as below?

		soc_gpio33_pq6 {
			nvidia,pins = "soc_gpio33_pq6";
			nvidia,function = "rsvd0";
			nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			nvidia,tristate = <TEGRA_PIN_ENABLE>;
			nvidia,enable-input = <TEGRA_PIN_ENABLE>;
			nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
			nvidia,lpdr = <TEGRA_PIN_DISABLE>;
		};

[jost38]

The padctl register for the pin is set to 0x54. Meaning:
E_SCHMT: DISABLE
GPIO_SF_SEL: GPIO
E_LPDR: DISABLE
E_LPBK: DISABLE
E_INPUT: ENABLE
E_IO_HV: DISABLE
TRISTATE: TRISTATE
PUPD: PULL_DOWN
PM: RSVD0

The ENABLE_CONFIG and OUTPUT_CONTROL registers are both set to 0x01.

I have measured this behavior on Pin 7, 22 and 23 however pins 7 and 23 are not only/directly connected to the shifter and module but still behave the same.
Pin 16 with no level shifter directly to the Module behaves as expected, with both pull up or pull down.

[Trumany]

@jost38

I have measured this behavior on Pin 7, 22 and 23 however pins 7 and 23 are not only/directly connected to the shifter and module but still behave the same.

I don’t get what you mean. Pin7, 22 and 23 are all connected to level shift.

[jost38]

From the pdf “P3737_A05_OrCAD_schematics(base_version)” from 25-OCT-2023 you can see that PIN7 Signal name “MCLK05_LVS” also has a Capacitor (c440 220pf) to ground next to its resistor (166 1M).
And Pin 23 Singal name SPI_SCK_LVS and SPI1_SCK_40PIN on the other side of the level shifter splits on the 1.8V side to the Signal CAM_SPI_SCK.
This may change the behavior when compared to other Signals who don’t have those alterations.
But since these differences are pretty minor in don’t think they have a big impact