Connecting Jaxier NX developer kit Display port output into XILINX (FPGA) DP core

We want to receive Jetson’s output from DP in Xilinx FPGA evaluation board (VCU118).
When we connect the Jetson to regular screen with DP it works.
When we connect video stream from the following video sources to Xilinx FPGA, it works:
a. PC (using NVIDIA Quadro P620 GPU)
b. Screen which acts as a repeater (NVIDIA JETSON XAVIER NX → screen → Xilinx FPGA)

But when we connect Jetson’s output (DP) to Xilinx FPGA it fails.
When we connected a DP sniffer we saw that the system completes training on all 4 lanes, but then the source (Jetson) sends a power down command and restarts the training.
Why it happenes and how we can fixed it?

Xilinx evaluation Board (VCU118) Kintex UltraScale+ - implemented with Xilinx example design and using the Display Port 1.4 RX Subsystem (2.1).

Sniffers data can be found at this file:
JETSON2VCU118.html (2.4 MB)

Thanks

Could you check if devkit has the same behavior with DP monitor? I remember this is normal behavior that even happens on monitor case.

Also, this is jetson TX2 forum but not NX forum.

When we connect the Jetson to regular monitor with DP it works.
Sorry for wrong forum, i moved the topic to Jetson NX forum.

I didn’t mean it would work or not. Of course it would work.

My point is below behavior would happen on monitor case too.

“but then the source (Jetson) sends a power down command and restarts the training.”

No, the training finished and the monitor works and we can see Jetson’s output.
I attached sniffers log for monitor conection too:
Jetson_to_monitor.html (224.4 KB)

Could you share the dmesg with your FPGA connected?

Just to be sure, you mean to call “dmesg” command on jetson when it connected to the FPGA. Am i write?

You can share

  1. Dmesg when you use normal DP monitor.

  2. Dmesg when you use the FPGA. Am.

Attached both logs.
We can see in the log file “dmesg_FPGA.txt” at the end of the file that the Jetson performed a power down.
dmesg_monitor.txt (66.4 KB)
dmesg_FPGA.txt (146.0 KB)

15200000 is for another head. Your DP looks like on 15210000. Please disable unused head first.

Also, please give me full dmesg. No need to parse log by yourself.

I just connected the DP output, the HDMI isn’t connected at all.
How can i disable the unused head?

Desciption of the attached logs production:

  1. I connected the jetson DP output to monitor.
  2. Turned on the jetson
    3, Ran “dmesg -t” command.
  3. I connected the same DP cable to the FPGA instead of the monitor
  4. Ran again “dmesg -t” command.

Do you mean in producing the full dmesg that i will turn on the jetson when it is connected to the FPGA and run the command?
Or I can perform all the step above without step #3?

Is this still the devkit? If so, then no need to disable unused head.

Please dump log which contains below sceanrio

  1. Boot up jetson with your DP cable connected.
  2. After system boots up, hotplug the DP cable.
  3. Just use “dmesg” to dump the full log and attach it here.

It is still devkit.
The output of the dmseg is attached:
dmesg_Monitor_2_FPGA.txt (213.8 KB)
Just to be sure i did the following:
i connected the jetson to monitor, turned it on and then connected the same DP cable from monitor to FPGA and run “dmesg”.

Is this unplug event done by you or it happened by itself automatically?

[Mon Aug 2 15:24:28 2021] tegradc 15210000.nvdisplay: dp: unplug event received
[Mon Aug 2 15:24:28 2021] hpd: state 4 (Enabled), hpd 0, pending_hpd_evt 1
[Mon Aug 2 15:24:28 2021] hpd: switching from state 4 (Enabled) to state 5 (Wait for HPD reassert)
[Mon Aug 2 15:24:28 2021] hpd: state 5 (Wait for HPD reassert), hpd 0, pending_hpd_evt 0
[Mon Aug 2 15:24:28 2021] hpd: DC from connected to disconnected
[Mon Aug 2 15:24:28 2021] dp lt: state 5 (link training pass), pending_lt_evt 1
[Mon Aug 2 15:24:28 2021] dp lt: switching from state 5 (link training pass) to state 0 (Reset)
[Mon Aug 2 15:24:28 2021] dp lt: state 0 (Reset), pending_lt_evt 0
[Mon Aug 2 15:24:28 2021] dp lt: link training force disable
[Mon Aug 2 15:24:28 2021] dp lt: switching from state 0 (Reset) to state 4 (link training fail/disable)

It happened by itself atumatically.

I don’t think this is software side issue.

You could compare the log with your monitor case. We don’t receive an extra unplug event when using normal monitor to test.

We tried to compare, but don’t understand all the AUX data that we received. This is actually the reason why I opened this post. Maybe there’s some configuration i can do on the Jetson side to work with Xilinx DP core. Or maybe there’s a kwown issue at Nvidia or Xilinx to work together.

Did anyone connect the DP output to Xilinx DP core and it worked?

Sorry that we don’t know. Maybe other users can share their experience.

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