I am trying to use the Design for Debug (DFD) architecture to capture the activity of one of the processor elements. Due to the constraints of this project, I cannot rebuild the kernel with the CoreSight flags enabled. I am able to do direct memory writes and reads. Using the NVIDIA Orin Series SoC technical reference manual (ID: DP-10508-002) with the provided base addresses and the corresponding manuals for the ETMs, funnels, and ETF (TMC) for the offsets, I can successfully manipulate and configure these modules. Meaning, I can write and read the registers in ways that correspond to the documentation.
My goal is to route the trace packets from the ETM to the ETF, filling its buffer, and then read out the packets from the ETF. I have followed the suggested configuration for the ETM in section 4.5 of the Arm Embedded Trace Macrocell Architecture Specification (ID 101923), the configuration for the ETF in section 2.2.2 of the CoreSight Trace Memory Controller (ID010111), and opening all of funnels in between.
With this configuration, I see no trace packets collect in the ETF. The ETF write data pointer does not increment despite incurring obvious events on the ETM’s processing element. I do not even see informational packets collect.
Is there some other module/register I need to configure in the Jetson Orin to enable before trace packets will flow? Is there some other reference or example I have missed?
That is an interesting thread but I am having difficulty applying it to my situation for a couple reasons.
The first is that the ETR is further downstream from the ETF. The technical reference has the flow: ETM > Cluster 0 Funnel > CCPLEX TOP Funnel > Major Funnel > ETF > Replicator > ETR. So right now I am not seeing any packets reaching the ETF so I don’t see how adjusting the carveout and write control for the ETR will impact the ETF.
The second is that I believe the thread is making use of a kernel with the CoreSight extensions enabled based on how the references to the registers are written.
The second point does suggest if I can be pointed to the relevant source code (kernel, example, etc.), maybe I can translate the references to the correct memory location and value.
We don’t validate it on Orin NX and Orin Nano developer kits, so it is possible it does not work on the two platforms. Do you use JTAG or ARM DStream and enable CoreSight? And ETM works but ETF fails?