Correction in Effects of misaligned accesses : Best Practices Guide 3.0

Hi all … I feel that there is mistake in Best practices guide 3.0 pg 24 … The para says

On the NVIDIA GeForce GTX 280 device, this results in an effective bandwidth of between 120 GBps for a single transaction and 70 GBps for two transactions per half warp. The number of transactions issued for a half warp of threads depends on the offset and whether the warp is even- or odd-numbered. For offsets of 0 or 16, each half warp results in a single 64-byte transaction (Figure 3.4). For offsets of 1 through 7 or 9 through 15, even-numbered warps result in a single 128-byte transaction (Figure 3.5) and odd-numbered warps result in two transactions: one 64-byte and one 32-byte (Figure 3.6). For offsets of 8, even-numbered warps result in one 128-byte transaction and odd-numbered warps result in two 32-byte transactions. The two 32-byte transactions, rather than a 64- and a 32-byte transaction, are responsible for the blip at the offset of 8 in Figure 3.7.

I think the underlined part must speak about even-numbered 1/2 warps and odd-numbered 1/2 warps instead of even-numbered warps and odd-numbered warps