Could I use "PCI VDM" on Orin Series?

[sumin.lee1]

Hello,

We wanna use the function “PCI VDM(Vendor Defined Message)” on Orin Series.
How to use it by ourselves?
Is the following link correct solution of our requirement?
And could I it use on Orin Series?

Server Management / libmctp · GitLab

[sumin.lee1]

I’ve found more proper documentation.
DSP2038 and MCTP over SMBus/I2C

Reference : MCTP on Linux introduction - Code Construct

MCTP Core Protocol is applied as minimum Linux Kernel 5.15.
Maybe , it is included in JetPack 6.

But, we should use I2C function for MCTP over PCIe, and it is included as minimum Linux Kernel 5.18.

Does it means, Could we not use “PCI VDM” on Jetson series ??

[kayccc]

Sorry for the late response.
Below is the comment from our internal team as your reference:

We didn’t verify this feature because we didn’t find any VDM supported EPs during our device bring up.
However, you can ask customer to try out, refer to self-explanatory register PCIE_RP_APPL_VDM_MSG_* below.
Using these registers and comparing with PCIe spec, customer should be able to verify it.

PCIE_RP_APPL_VDM_MSG_0_0

Register space mapped for different vendor message header fields. The mapping is as follows
ven_msg_len → ven_msg_hdr0[9:0];
ven_msg_fmt → ven_msg_hdr0[11:10];
ven_msg_attr → ven_msg_hdr0[13:12];
ven_msg_ep → ven_msg_hdr0[14];
ven_msg_td → ven_msg_hdr0[15];
ven_msg_func_num → ven_msg_hdr0[18:16];
ven_msg_tc → ven_msg_hdr0[22:20];
ven_msg_type → ven_msg_hdr0[28:24];
ven_msg_code → ven_msg_hdr1[7:0];
ven_msg_tag → ven_msg_hdr1[15:8];
ven_msg_data → {ven_msg_hdr3,ven_msg_hdr2}

Offset: 0x9c
Read/Write: R/W
Parity Protection: N
Shadow: N
SCR Protection: 0
Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit	Reset	Description
31	0x0	VEN_MSG_REQ_STATE:
HW-CLEAR : When set to 1, VDM message will be transmitted using the fields VEN_MSG_HDR0/1/2/3.
30:0	0x0	VEN_MSG_HDR0:
{ven_msg_type[4:0],1’b0,ven_msg_tc[2:0],1’b0,'ven_msg_func_num[2:0],ven_msg_td,ven_msg_ep,ven_msg_attr[1:0],ven_msg_fmt[1:0],ven_msg_len[9:0]}

PCIE_RP_APPL_VDM_MSG_1_0
Offset: 0xa0
Read/Write: R/W
Parity Protection: N
Shadow: N
SCR Protection: 0
Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit	Reset	Description
31:0	0x0	VEN_MSG_HDR1:
{ven_msg_tag[7:0],ven_msg_code[7:0]}

PCIE_RP_APPL_VDM_MSG_2_0
Offset: 0xa4
Read/Write: R/W
Parity Protection: N
Shadow: N
SCR Protection: 0
Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit	Reset	Description
31:0	0x0	VEN_MSG_HDR2:
VDM Payload Lower DWORD

PCIE_RP_APPL_VDM_MSG_3_0
Offset: 0xa8
Read/Write: R/W
Parity Protection: N
Shadow: N
SCR Protection: 0
Reset: 0x00000000 (0b0000,0000,0000,0000,0000,0000,0000,0000)

Bit	Reset	Description
31:0	0x0	VEN_MSG_HDR3:
VDM Payload Upper DWORD

[sumin.lee1]

Thank you for response.
We will check it with ep device vendor.

[sumin.lee1]

It looks “MCTP over PCI” isn’t applied in the Linux kernel 5.15.
There is some possibility that the following code could work if migrated to the L4T source code.

I think the following device tree will function after the code migration.

We will check it in the near future
I will let you know if there is any progress.

Thank you for the support.