Could you let us know the worst Case Carrier Board PCB Delay (ps) for PCIe Gen4 ?
Could you let us know the worst Case Carrier Board PCB Delay (ps) for PCIe Gen4 ?
Sorry for the mistake, it is up to Gen4 as listed in Design Guide. And also you can refer to the 7.2.2 PCIe Gen4 Design Guidelines for routing requests.
No problem. on same page.
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