CPU power gated modes

Hello, I have an application for the TK1 where I need to run the ARM cores at their max speed for a burst of time (say 300ms every second) and then for the rest of the time I’d like them to be at their lowest power level possible for power / thermal reasons. After running the application for a bit, I ran cat /sys/devices/system/cpu/cpu*/cpuidle/state*/* to see the power states the CPUs go in.

Summary is they never go into power down mode - they just go into the mode where the clock is gated. I assume we’d save quite a bit more power if they went into power down mode. The wiki that talks about power management doesn’t cover this at all. Is there any reason they wouldn’t go in power down mode? It isn’t disabled from what I can tell.

Here is the cpuidle data I get:
Desc, Disabled, Latency, Name, Power, Residency, Time, Usage
CPU 0
State 0:
CPU clock gated, 0, 10, clock-gated, 600, 10, 831686793, 2102187
State 1:
CPU power gated, 0, 500, powered-down, 100, 1000, 0, 0
State 2:
MC clock stop, 1, 3500, mc-clock, 0, 5000, 0, 0

CPU 1
State 0:
CPU clock gated, 0, 10, clock-gated, 600, 10, 820555790, 358967
State 1:
CPU power gated, 0, 500, powered-down, 100, 1000, 0, 0

CPU 2
State 0:
CPU clock gated 0, 10, clock-gated, 600, 10, 823785034, 330753
State 1:
CPU power gated 0, 500, powered-down, 100, 1000, 0, 0

CPU 3
State 0:
CPU clock gated, 0, 10, clock-gated, 600, 10, 788798060, 316111
State 1:
CPU power gated 0, 500, powered-down, 100, 1000, 0, 0

Are you using Jetson Devkit for your experiment? is display connected and ON while checking the status? LP0 or LP1 is the power off state. However, if there is any activity in the system, it will prevent it from entering that low-power state.

Chapter 9 of TRM provides power states and power-gating information.

Thanks. This was on a dev kit. It turns out uboot didn’t provide the vector for getting out of that power state, so it was disabled.