Create a dts with "camera-control-output-high" on Jetson Thor

[Amber.Tsai]

Hi,
我在 t264/nv-public/overlay/ 目錄下新增了 tegra264-p3971-camera-customized-camera_1.dts。
我需要將 CAM0_RST_L & CAM0_PWDN 設為 high，所以我設定了camera-control-output-high。
在我選擇我的 device tree 之前，我使用 cat /sys/kernel/debug/gpio 確認了 CAM0_RST_L & CAM0_PWDN 狀態為 low.。
我選擇我的 device tree 並 reboot 後，再次使用 cat /sys/kernel/debug/gpio 確認 CAM0_RST_L & CAM0_PWDN 狀態，但我卻無法看到 gpiochip2 了。
若我將 camera-control-output-high改成camera-control-output-low。再次使用 cat /sys/kernel/debug/gpio 確認 CAM0_RST_L & CAM0_PWDN 狀態，就能再次看到CAM0_RST_L & CAM0_PWDN 狀態為 low.。
可以幫我確認下這個問題嗎?

[JerryChang]

hello Amber.Tsai,

would you like to have GPIO pin initial state as high? active low when toggle the pin state change?

[Amber.Tsai]

@JerryChang

would you like to have GPIO pin initial state as high? active low when toggle the pin state change?

Dear @JerryChang , yes, I need both GPIO pin initial state as high. It seems be low currently.

[JerryChang]

hello Amber.Tsai,

you may refer to developer guide, Change the Pinmux to update the pin settings.

[p.bergin]

@JerryChang

you may refer to developer guide, Change the Pinmux to update the pin settings.

@JerryChang for reference and your info:

Some GPIO can't not be used?

Hi NV_Team, Where to find the memory address for GPIOs, so we can use devmem to check it. like this topic

Thor SoC TRM Missing Programming Guidelines

Thanks to NVIDIA for finally releasing the Thor SoC Technical Reference Manual. However, is anyone else frustrated that it doesn’t include a Programming Guidelines section, unlike the Orin SoC TRM? Without those guidelines, the Thor TRM ends up being little more than function description and block diagrams, making it far less useful for low-level bring-up and development compared to Orin. For example, where is the “Pad Control Grouping” table mentioned here? Are there plans to release the Prog…

The part in the documentation you reference to for Thor is not complete and not usable at the moment.

[KevinFFF]

Hi @Amber.Tsai,

@Amber.Tsai

yes, I need both GPIO pin initial state as high. It seems be low currently.

Please configure these 2 pins as following in pinmux spreadsheet for this use case.

@Amber.Tsai

我選擇我的 device tree 並 reboot 後，再次使用 cat /sys/kernel/debug/gpio 確認 CAM0_RST_L & CAM0_PWDN 狀態，但我卻無法看到 gpiochip2 了。

It is not the expected result to me that gpiochip2 is the GPIO controller for tegra264-gpio-main. Please share the full result when you hit this issue.

Hi @p.bergin

@p.bergin

The part in the documentation you reference to for Thor is not complete and not usable at the moment.

The PADCTL register will not be mentioned in Thor TRM as we wish customer just referring to our developer guide and use pinmux spreadsheet to configure the pinmux.