CSI Calibration registers -- Offset in code & TRM varies

Hi All,

In file, drivers/media/platform/tegra/mipical/mipi_cal.c,

In function, tegra_mipi_wait(), calibration registers are used. For e.g. CIL_MIPI_CAL_STATUS and
CIL_MIPI_CAL_STATUS_2.

Offset for these registers in code:

#define CIL_MIPI_CAL_STATUS 0x08

#define CIL_MIPI_CAL_STATUS_2 0x0c

In TRM, the offset is:

MIPI_CAL_CIL_MIPI_CAL_STATUS_0
CIL MIPI Calibration Status
Offset: 0xc | Read/Write: RO | Reset: 0xXXXXXXXX

29.2.5 MIPI_CAL_CIL_MIPI_CAL_STATUS_2_0
MIPI CLK Calibration Status 2
Offset: 0x10 | Read/Write: RO | Reset: 0x000000XX

In code and TRM, calibration registers offset differs. Which one is proper value?

-Thanks.

Thanks for you information.
Looks the REG offset should be different with TX2.

Please provide the modified code patch for this.

-Thanks.

@BalajiNP
The fact that TX1 and TX2 have different offsets is taken care of.
The ADDR() macro expands into offset + (csi_base), and csi_base is different for TX1, TX2.
TX2 is csi_base = 0, so offsets are written as-is. TX1, is csi_base= -4, so offsets are written at -4 of the offset.