Hello,
we developped a PCB to connect a Jetson AGX Xavier devkit to a Texas Instruments MMWCAS-RF-EVM Evaluation board which is made of four AWR2243 radar chipsets.
We control the radar chips through SPI and GPIO and that part is working well.
These chips have a CSI2 D-PHY interface to transfert radar data to a host, and we struggle to make this work. Each chipset has four RX channels, hence we plan to use the 4x4 CSI configuration to get all the 16 RX radar channels, but radar chips can be configured to use all or only one lane.
We saw a lot of topics related to AWR2243-Jetson CSI issues [1][2][3][4], but we didn’t find any solution to our problem.
The kernel is the latest one for this board: 5.10.216 (Jestson Linux 35.6.0).
To avoid any problem due to signal integrity we reduce the camera CSI clock frequency to 75MHz. The image size is 256x32 (16 bits per pixel).
We validated the radar CSI configuration with an oscilloscope. We can see the Start of Frame, Line Start, datas, Line End, …, Line Start, datas, Line End, End Of Frame.
Unfortunately we are unable to capture an image with V4L2.
1) 4 CSI lanes per radar chip
On the debug console we see a timeout whatever the radar chip. Please refer to
log_video0_4lanes.txt (1.1 KB)
On the traces we see interrupts and flags. However in the source code we did not find the meaning of those flags. Can you please analyse trace_videoX_4lanes.txt files trace_video0_4lanes.txt (502.8 KB)
trace_video1_4lanes.txt (526.2 KB)
trace_video2_4lanes.txt (546.6 KB)
trace_video3_4lanes.txt (526.2 KB)
and tell us what is going wrong on the CSI when 4 lanes are used?
2) 1 CSI lane per radar chip
On the debug console we see errors and then a timeout. Please refer to log_video0_1lane.txt
log_video0_1lane.txt (2.4 KB)
It looks like the problem is coming from the End Of Frame:
[ 208.569339] tegra-camrtc-capture-vi tegra-capture-vi: corr_err: discarding frame 0, flags: 0, err_data 131072
cap dqbuf: 0 seq: 0 bytesused: 16384 ts: 0.000000 (error, ts-monotonic, ts-src-eof)
err_data 131072 is 0x20000. It means bit #17 is at 1.
In nvidia/include/soc/tegra/camrtc-capture.h:
/* Frame end was forced by channel reset /
define CAPTURE_CHANNEL_ERROR_FORCE_FE MK_BIT32(17)
Can you please confirm this error? In that case what can be the root cause of such an error? At the oscilloscope everything seems to be fine.
On the traces the flags are not the same as the ones with 4 CSI lanes. Can you please analyse trace_video0_1lane.txt files
trace_video0_1lane.txt (1.4 MB)
and tell us what is going wrong on the CSI when 1 lane is used?
3) Device tree
Can you please check our device tree file for both configurations (tegra194-camera-e3326-a00-Xlane.dtsi)?
tegra194-camera-e3326-a00-1lane.dtsi.txt (12.7 KB)
tegra194-camera-e3326-a00-4lanes.dtsi.txt (12.7 KB)
4) Other questions
Is there any errata/limitations on the CSI controller?
We saw that RidgeRun has developped a driver for this AWR2243 chip [5], so there should not be any hardware limitation, unless the CSI controller has changed between Xavier generation and Orin generation ?
[4] https://forums.developer.nvidia.com/t/jetson-mipi-csi-2-timeout/266521/10
[5] https://developer.ridgerun.com/wiki/index.php/Texas_Instruments_AWR2243_Linux_driver