CSI2 clocks missed from CrossLink FPGA to Jetson Nano

Hello!

We have a custom board with CrossLink FPGA LIF-MD6000-6MG81I.FPGA do a conversion of the input video stream to CSI interface.

We are connecting our board to Jetson Nano CSI4 port (0,1 lanes) and it didn’t working…

We are observed that there are no CSI4_CLK, but CSI4_D0, CSI4_D1 looks alive.

If we are connecting this FPGA board to another our board with IMX8M cpu - all works fine, CSI_CLK amplitude is about 200mV single ended, frames are captured.

If we are connecting our board to CSI0 port (0,1 lanes) it’s also didn’t work, CLK amplitude about zero.

All I2C communication are cut out (sensor setup in front of FPGA are done by another cpu externally)

IMX219 CSI camera works well on Nano CSI0 port, as well as with our IMX8M board.

We have such errors:

[  334.539334] video4linux video0: frame start syncpt timeout!0
[  334.545363] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  334.545367] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[  334.545371] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[  334.545375] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040041
[  334.545412] vi 54080000.vi: cil_settingtime was autocalculated

Can you suggest any ways to solve this situation with CSI clocks?

Looks like it’s some kind of software initializations or timings issue…

Thank you in advance,
Roman Abakumov

It could be the MIPI timing issue.
Have a check the CSI_CIL_A_STATUS_0 REG from TRM to get more information.

CSI_CIL_A_STATUS_0 is for CSI0 Nano port, if we using CSI4 Nano port, then we should check CSI1_CIL_A_STATUS_0 reg, am i right?

CSI CSI0 A
CSI CSI1 B
CSI1 CSI4L C
CSI1 CSI4H D
CSI2 CSI2 E
CSI2 CSI3 F

Yes

CSI1_CIL_A_STATUS_0 is 0x00000010 wich is:
CILA_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11) instead of transitioning into the Escape mode or Turn Around mode (LP00)

CSI1_CILA_STATUS_0 is 0x00040041 wich is:
CILA_DATA_LANE1_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11) instead of transitioning

CILA_DATA_LANE0_CTRL_ERR: Control Error. Set when CIL-A detects LP state 01 or 10 followed by a stop state (LP11) instead of transitioning

CILA_CLK_LANE_CTRL_ERR: Control Error. Set when CIL-A detects incorrect line state sequence on clk lane

We can change this timings in IP core:

byteclock 37,125 MHz 26,94 ns
UI 594 MHz 1,68 ns
t_HS-PREPARE 3 cyc 80,81 ns
t_HS-ZERO 3 cyc 80,81 ns
t_CLK-PRE 1 cyc 26,94 ns
t_CLK-POST 6 cyc 161,62 ns

Can it help to resolve errors above? Which values can you recommend to change?

Confirm the pix_clk_hz was report correct and modify the cil_settletime = “0” for auto calculate the properly time.
Also can try discontinuous_clk = “yes”

Hello!
We do some research. We tried 2 FPGA firmwares with different timings (3,12,2,13), (3,4,2,7) and one more FPGA firmware with different CSI IP. All these variants works fine with IMX8 without any driver modifications and all these variants doesn’t work with jetson nano.

We observe some erros with FW0:

[ 1235.764099] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[ 1235.764103] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040

TEGRA_CSI_CIL_STATUS could be 0x00000011, 0x00000012, 0x00000013

We observe some erros with FW1:

[  109.932019] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000010
[  109.932023] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040

TEGRA_CSI_CIL_STATUS always 0x00000010

We observe some erros with FW2:

[  120.843134] video4linux video0: frame start syncpt timeout!0
[  120.843138] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  120.843142] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00004000
[  120.843144] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000012
[  120.843147] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00040040
[  120.843183] vi 54080000.vi: cil_settingtime was autocalculated
[  120.843186] vi 54080000.vi: csi clock settle time: 13, cil settle time: 10
[  121.047141] video4linux video0: frame start syncpt timeout!0
[  121.047146] video4linux video0: TEGRA_VI_CSI_ERROR_STATUS 0x00000000
[  121.047149] vi 54080000.vi: TEGRA_CSI_PIXEL_PARSER_STATUS 0x00000000
[  121.047152] vi 54080000.vi: TEGRA_CSI_CIL_STATUS 0x00000002
[  121.047155] vi 54080000.vi: TEGRA_CSI_CILX_STATUS 0x00000000
[  121.047192] vi 54080000.vi: cil_settingtime was autocalculated