CSI2- MIPI CSI2 CIL error bits set to High-Error conditions?

We are seeing below error bits set to High by TX1. Can we know the error conditions-which can cause these bits set to High?

Attached MIPI CSI2 Register dump for nVIDIA review

Left Camera:
Below error bits are set in these registers
Offset :0x193c : CSI2_CSI_CIL_A_STATUS_0
Bit(1): CILA_SOT_MB_ERR: set to High

Offset 0x1940: CSI2_CSI_CILA_STATUS_0
Bit(5):CILA_DATA_LANE0_SOT_MB_ERR: set to high

Right Camera:
Below error bits are set in these registers
Offset :0x1970 : CSI2_CSI_CIL_B_STATUS_0
Bit(1): CILB_SOT_MB_ERR: set to High
Offset 0x1974: CSI2_CSI_CILB_STATUS_0
Bit(5):CILB_DATA_LANE0_SOT_MB_ERR: set to highcomplete_MIPICSIreg_dump_nVIDIA_review.txt (14.2 KB)

It’s could be the signal cause this error.
Have a check MIPI signal first.

Hi,

I could n’t see any emphasis/equalization settings in MIPI registers for CSI Interface. Can you suggest register setting to avoid below issue on CSI?

“CILA_DATA_LANE0_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi
bit start of transmission byte error in one of the packets SOT bytes on data lane-0. The packet will be
discarded.”

I mean the problem is the sensor output signal have problem. You may need HW engineer to check also consult with sensor vendor to confirm the setting.

Hi Shane, Please confirm below:

  1. DPHY used in TX compliant to 1.1 or 1.2?
  2. CSI RX has equalizer or not?

Get the detail information from below link.

Hi,

As you know , we have below issue

“CILA_DATA_LANE0_SOT_MB_ERR: Start of Transmission Multi Bit Error. Set when CIL-A detects a multi
bit start of transmission byte error in one of the packets SOT bytes on data lane-0. The packet will be
discarded.”

We have modified OV9732(Camera sensor) DPHY Timing registers below to the maximum values. Now we are “not” seeing Start of Transmission Multi Bit Errors after 24 hours of testing.

CLK_Prepare_Max - Set to Maximum value
HS_Prepare_Max- Set to Maximum Value
HS_ZERO_MIN- Set to higher value

Curretly data lane is operating at 360Mbps and FR4 PCB trace length close to 6-7 inch(between TX1 and Camera sensor)

Please let us know the TX1 recommendations above mentioned timing parameter( CLK_Prepare, HS_Prepare and HS_Zero_Min duration for 360Mbps single data lane using 6-7inch PCB trace.

hello sreenivasa.potnuru,

you should also check Camera Hardware Design Guides for recommendations and guidelines.
thanks