CUDA manual mismatch: Shared memory bank Bandwidth

Hi,

CUDA C programming guide, section G.4.3 (page 177) :

"Shared memory has 32 banks that are organized such that successive
32-bit words are assigned to successive banks, i.e. interleaved.
Each bank has a bandwidth of 32 bits per two clock cycles."

CUDA Best Practices guide, section 3.2.2.1 (page 35):

“Shared memory banks are organized such that successive 32-bit words
are assigned to successive banks and each bank has a bandwidth of 32 bits per clock cycle.
The bandwidth of shared memory is 32 bits per bank per clock cycle.”

So what is correct now?