Custom TK1 board with x1 PCIE connected to FPGA PCIE interface

I am using PCIE controller 0, lane PEX_TX4 and PEX_RX4, as the x1 for this one lane PCIE interface but I don’t seem to be getting a clock on the PEX_CLK1_P/N lines. Any ideas on what I might be missing? I followed the design guide on how to connect all the PEX pins.

I am not 100% sure on the pin PEX_WAKE_N if it’s unused. I have it pulled up to 3.3V at the moment because I referenced the Jetson board but I am beginning to think it should be NC if it’s unused?

I am also not quite sure about pin PEX_L0_CLKREQ_N. I know that’s a signal from the PCIE device (the fpga in my case). Does this signal have to be asserted low then go back high? Or can it just be pulled low and held low indicating that the device needs the PEX_CLK1.

Still looking for help on this but a quick update.

I have ruled out the PEX_WAKE_N and PEX_L0_CLKREQ_N signals as the source of the problem. I narrowed the reason for not having a PEX_CLK1 signal due to the Tegra booting first then the FPGA is programmed by the Tegra. However, since the FPGA is not programmed during kernel boot where the initial PCIE scan happens, there are no devices so the Tegra puts the PCIE controllers into low power mode (turning off the clks). At least this is what I think is happening if I am interpreting the software correctly.

Is there a way to get the PCIE controllers to “turn back on” and re-scan the bus for PCIE devices after the kernel boots and I have programmed the FPGA?

I have already tried holding the Tegra in uboot, program the FPGA then boot into the kernel, but it appears that during kernel boot, the PMIC for the Tegra resets and it kills the power to the FPGA (I am using the TK1’s PMIC) to control the power on for the FPGA as well.

Hi rccola75,

Basically PEX_WAKE_N is used to activate the PCIE main power rails and reference clocks. Did you try asserting it after kernel boot up?

Thanks for responding, Trumany. When you say I should try asserting PEX_WAKE_N after the kernel boots up and FPGA is programmed, do you mean pulling it low then release it back high?

Also, when you say that PEX_WAKE_N is used to activate the PCIE main power rails and reference clocks, are you referring to the PEX_CLK1 and PEX_CLK2 clock signals. There is actually a PEX_REFCLK_P/N that the embedded design guide says should be grounded (although the Jetson TK1 reference board has them as NC).

When I was debugging this issue yesterday, I connected a jumper wire from PEX_WAKE_N to ground so it’s currently held low, but there is a 100K pull-up to 3.3V just like the Jetson TK1 reference board has the PEX_WAKE_N pin.

You can check the connections in chapter 3.4.2 of design guide, PEX_L0_CLKREQ_N is used to request PEX_CLK1.Leaving PEX_REFCLK as NC is ok.
As you said the FPGA is powered up later than TK1, so the PEX_WAKE_N is needed before it requests clock.

Did you try booting up a while and then pull WAKE to ground and keep it low then? (Not pull down too early)

At the moment, the FPGA commands the PEX_L0_CLKREQ_N low after it is up and programmed. The PEX_WAKE_N pin is hard tied to ground so it is definitely low before PEX_L0_CLKREQ_N is asserted low. Do you think that the PEX_WAKE_N pin is low too early? If I am understanding your last reply correctly, I should use this order: boot up the Tegra -> program the FPGA -> pull down PEX_WAKE_N -> pull down PEX_L0_CLKREQ_N ?

I am not sure if this is important but just wanted to point out that on the Jetson TK1 reference board, the PEX_CLK1 and PEXCLK2 are both functioning right after boot even with PEX_L0_CLK_REQ_N floating and PEX_WAKE_N pulled up. I am guessing during the initial kernel boot the PCIE scans and sees the Realtek device on the PEX_CLK2 PCIE controller so it never goes to sleep, and the PCIE clocks on both controllers work. I checked the clocks on the o-scope. Is this the correct assumption?

The sequence of booting up the Tegra -> program the FPGA -> pull down PEX_WAKE_N -> pull down PEX_L0_CLKREQ_N did not work.

Just a quick update. I was finally able to get this to work by booting up the processor, keep it in u-boot, program the FPGA, then boot the kernel. After doing that, the FPGA’s pcie device was able to be detected by the TK1’s PCIE controller.

I know there is a way to use a GPIO and turn on the hot plug feature on the TK1 so I will give that a shot next.

Is it possible to program the FPGA with the Tegra in u-boot?